AM263P4: Motor Control Synchronisation between currents(SDFM) and angle(Resolver)

Hi Marcel,

Please find my responses below

Marcel Pfeifer said:

i imagine the resolver value is sampled at the maximum of excitation PWM. Am i rigth with this?

Yes, that is true, the Resolver ADCs sample at the maximum of Excitation component in the modulated Sine and Cosine signals. Since there can be any phase delays between the actual Excitation signal to the Excitation component in the Sine and Cosine signals, this is taken care by the RDC via Auto Sample Time Select. These delays can be due to Amplifier and Board introducing these delays. Please refer to Section 7.5.3.2.2.1.4 Auto Sample Time Select and the section above Figure 7-176 or AM263P Technical Reference Manual for more information.

Marcel Pfeifer said:

Also i don't have any data rdy interrupt. So iam not sure when exactly i have new data. 

I will get back to you on this.

Marcel Pfeifer said:

I tried to check examples to get a better understanding but this gets me confused even more.

I will ask my colleague to answer for this. Please give us some time.

Thanks,

Tejas Kulakarni

Hi Marcel,

Apologies for the delay. We have reached out to our internal design teams for some answers. We will revert back to you when we have those answers(mostly by end of this week).

Thanks,
Tejas Kulakarni

Hi Marcel,

We ran few internal design simulations for getting accurate numbers and the below are the results we could get.

• ADC Start of Conversion to Digital data available from ADC, takes about 360ns
• ADC Data available to Angle from Arctan result, takes about 220ns
• ADC Data available to Velocity(from track2 loop) result, takes about 460ns

These values would change based on different configurations of the resolver used. I hope these above values would help you setup your Motor Control loop. I would suggest to setup the Motor loop with some considerable margins above these times.

Please do let me know if any further details are needed. Do let me know if these details are not exhaustive enough.

Thanks,

Tejas Kulakarni

Hi Marcel, 

The ideal sample module you are suggesting is responsible to select a sample out of the OSR samples. there are 4 modes, of which 3 are auto modes to select the sample, 4th is manual mode where the override value is directly considered to be ideal one. the ideal sample is actually function of the signal path delay, which is specific to board design. so are the phase / gain correction values. hence once these are found out from the auto modes, we can turn the estimations / auto loops and use them as the override / manual values to save power consumption from the IP. 

thanks and regards,

Madhava

Hey Tejas, hey Madhava,

Tejas Kulakarni said:

• ADC Start of Conversion to Digital data available from ADC, takes about 360ns
• ADC Data available to Angle from Arctan result, takes about 220ns
• ADC Data available to Velocity(from track2 loop) result, takes about 460ns

you got nice data here, what are your settings of the resolver module?
Can you explain me your test setup?

Back to the general timings. If i have no bottom sampling enabled my updaterate of the resolver module is 20kHz (excitation frequency = 20kHz). Is there any interrupt that informs me that new data is available, or do i have to set a timer to poll a value out of the Resolver module every 50µs? 

Can you answer my questions regarding the example?

Marcel Pfeifer said:

I tried to check examples to get a better understanding but this gets me confused even more. 
I'm relating to this example: https://software-dl.ti.com/mcu-plus-sdk/esd/AM263PX/10_00_00_35/exports/docs/api_guide_am263px/EXAMPLES_DRIVERS_RESOLVER_ANGLE_SPEED.html
It says: The ADC SoC start Delay is set at 20, i.e., 20*1250nS +30nS or, 25.030 uS. First of all i cant find this configuration in the related sysconfig. There it's set to zero:

then it implies that i have to set the sample timing manually? I thought the ideal sampling time module is in charge of the sampling time?

What is the Ideal Sample Overwrite value of 7 used for?

Best regards

Marcel

Hi Marcel, 

SoC Delay is delay from excitation frequency start to the initial SOC trigger onto the ADCs ( we are working on getting better information to resolve confusions and will update the TRM with them). There may have been a documentation error, thanks for pointing out, we will take an action to clear it up in the example docs.

Override value of 7 was used with the manual ideal sample mode, because in the setup we had for the resolver example, gave the path delay for the resolver signals. the auto mode resulted in 7th sample of the OSR 20 samples being ideal sample. hence, we chose it in the example.

thanks and regards,

Madhava