Tool/software:
hi TI Expert,
I am triggering an ADC interrupt at a certain frequency (say 1ms). Sometimes, my ISR takes longer than 1ms to execute. In this case, I am seeing that the next interrupt scheduled to be triggered at 1ms is missed until the ISR completes it's execution.
Could you please advice how to configure the interrupt so that the ADC interrupt scheduled at 1ms is not missed even if the previous ISR overruns? I am looking to implement the use case where the ADC interrupt triggers every 1ms, if the ISR is overrun, then the execution gets back to running the overrun ISR after executing the newly triggered interrupt.
Current Implementation Details:
HwiP_Params_init(&hwiPrms);
hwiPrms.intNum = CSLR_R5FSS0_CORE0_CONTROLSS_INTRXBAR0_OUT_1;
hwiPrms.callback = Sys_Adc_Isr;
hwiPrms.priority = 8;
hwiPrms.isPulse = TRUE;
hwiPrms.isFIQ = 0;
(void) HwiP_construct(&HwiObject, &hwiPrms);
ADC_clearInterruptStatus(ADC2_BASE_ADDR, ADC_INT_NUMBER1);
void Sys_Adc_Isr(void *handle)
{
ADC_clearInterruptStatus(ADC2_BASE_ADDR, ADC_INT_NUMBER1);
// ISR logic here
return;
}
I am running the ISR from TCM memory. This is the only ISR currently being triggered in the system, so I guess priority of 8 should not matter.
Looking forward to your inputs. Thanks!
