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AM2634: Arm-based microcontrollers forum

Part Number: AM2634


Tool/software:

Hello.  We have an application that requires an AM263 to be mounted on a power electronics board with thick copper layers, with all layers having 2oz copper minimum although 4oz is desirable.  There are minimum trace/space requirements for such boards.  Our manufacturer tells us they can do no less than 4.5mils with a 2oz board.

The AM263 BGA ZCZ requires very small traces and clearances for proper fanout, as well as filling copper pours for thermal management.  One example is shown below, which is an image of fanout on Layer 3 for the TI Control Card.  Here, there are 4mil traces, 4.5mil spacing between trace and nearest via, with vias having 8mil drills and 18mil diameters.


To achieve 4.5mil trace/space, it seems that the only solutions are the following:
* Expand the PCB to many more layers, with 1oz layers reserved for the BGA and >2oz layers reserved for power.  This is obviously very costly.
* Reduce the BGA via drill size from 8mil down to perhaps 6 mil (0.15mm).  

Reducing the drill size might affect thermal performance and TI recommends maximizing this where possible, according to the hardware design guide.
Note:  our PCB is 2mm thick.

My questions are:  
Is TI familiar with designs placing this BGA on such boards? Does TI recommend a different solution from those posed above?  
If we do reduce drills to 6mil, is there a reason to believe the package cannot be adequately cooled?  Note that we will not be running this device at its maximum processing power level.


  • Jeff,

    The two main concerns with reducing via drill size from 8mil to 6mil are thermal risks and increased cost. Reducing the drill size by 25% means a 25% decrease in metal for signal connectivity and thermal conductivity.

    Any deviation outside of what TI recommends assumes risk since we have not proven any solutions outside of our recommended specs.

    Regards,

    Brennan

  • Thank you for the response.  
    I acknowledge the risks of reducing the drill size to 6mil.

    Outside of drills, is TI aware of any other solutions that customers have used to place this device on a 2oz copper PCB?  I'm wondering if mixed copper weights across different layers or localized copper weights on the same layer has been tried, or other more creative solutions.

  • Hi Jeff,

    I'm not aware of any specific solutions customers have implemented for this MCU on 2oz Cu PCB. We typically do not offer 'full' layout reviews, and can only suggest what we have outlined in our Hardware Design Guidelines since the implementation documented has been proven to meet all required device specifications.

    Regards,

    Brennan