SYSCONFIG: Background for changed parameter on DDR configuration tool

The parameters you mentioned were optimized based on some internal debug that was performed and updates to DFI timing formulas in the IP documentation.  The parameters are associated with internal DFI timing between the controller and PHY.    

Regards,

James

Hello,

Thank you for your reply.
Let me confirm about below as well.

Q1. 
>updates to DFI timing formulas in the IP documentation.
You said above in previous thread, but which IP did you point out controller or PHY ?
And is it TI's IP or 3rd party's one ?
(I would like to confirm why IP document was updated.)

Q2.
>The parameters are associated with internal DFI timing between the controller and PHY.   
Do these parameters affect data read/write to DDR memory ?

Best Regards,

Q1. The DFI is the interface between the controller and PHY.  The updates to the registers were in the controller and PI (Phy Interface module), but were based on updates in the PHY documentation.  The updates were provided by the IP vendor to fix errors in the doc, this was not the only change  . The DDR controller and PHY is 3rd party IP.  

Q2, Not really, these are just associated with the internal communication within the IP.  They would not result in the failures you are seeing.  Note that these values were optimized based on the updates from the IP vendor, the changes were not a result of errors we were seeing in characterization.

Regards,

James

Hi James,

Thank you for your reply.
Understood.

By the way, how about "wrlvl_delay_early_threshold_X" parameter ?
Do these parameter affect data read/write ?

Best Regards,

No, this parameter facilitates write leveling training algorithm.  

Most likely the rx_pclk fix may be helping your design, as this internal clock was found to be too slow in earlier configuration, and helped fix an issue at higher temps.  But there were several changes from 0.8.80 that are probably attributing to more stable performance.

Has the customer tested across full operating temperature?

Regards,

James

Hi James,

>Has the customer tested across full operating temperature?
=> They performed test accross -20 to 60 degree (This is customer's usecase).
However, the error which I mentioned first thread "failare rate : 6(error number they observed) / 120(total number they tested" was performed under nominal temperature (25 degree.).

>Most likely the rx_pclk fix may be helping your design, as this internal clock was found to be too slow in earlier configuration, and helped fix an issue at higher temps.
=> Which register's setting will affect above "rx_pclk" ?

>But there were several changes from 0.8.80 that are probably attributing to more stable performance.
=> I summarized dtsi file difference in xls. I will send it via "private message" to you.
As I checked this list, I suspected change of following register's (I posted in this thread) setting are most affected to this customer's problem.

1. "TDFI_RDDATA_EN_FX" (X = 0,1,2) v0.08.80 ; 0x0C -> v0.10.32 ; 0x08
2. "TDFI_WRCSLAT_FX" (X = 0,1,2) v0.08.80 ; 0x0A -> v0.10.32 ; 0x06
3. "TDFI_PHY_WRLAT_FX" (X=0,1,2)  v0.08.80 ; 0x09 -> v0.10.32 ; 0x05
4. "PI_RDLAT_ADJ_FX" (X=0,1,2)  v0.08.80 ; 0x0D -> v0.10.32 ; 0x09
5. "PI_WRLAT_ADJ_FX" (X=0,1,2)  v0.08.80 ; 0x0A -> v0.10.32 ; 0x06
6. "PHY_WRLVL_DELAY_EARLY_THRESHOLD_X" (X=0,1) v0.08.80 ; 0x1A0 -> v0.10.32 ; 0x100

However, if you have another comment, could you please let me know ?

Best Regards, 

If you do a diff of the full configuration file, I think you should find several more differences than what you list above.  

I guess i failed to ask if this is a DDR4 or LPDDR4 design?  There are different optimizations for each.

James

Hi James,

Thank you for your reply.

>If you do a diff of the full configuration file, I think you should find several more differences than what you list above.  
=> OK, I will send original dtsi file to you via private message.

>I guess i failed to ask if this is a DDR4 or LPDDR4 design? 
Customer use DDR4.

Best Regards,

Hi James,

I have taken over this case from Ryuuichi due to some circumstances.
I have also been shared the data that Ryuuichi sent you via private message. 
Could you please reply to this thread after confirming the data.

Best Regards,
Kanae

Hi Kanae, sorry i missed this in my email.  I will look over the files tomorrow.

regards,

James

Ok, i confirmed the two files have many more differences than the xls file.  But most likely the value in PHY_1371 was the optimization which is helping to avoid the errors from the original file

Regards,

James

Hi James,

Thank you for your reply.

James said.
most likely the value in PHY_1371 was the optimization which is helping to avoid the errors from the original file

Regarding the above comment, what is the reason of your decision to do so?

Also, can you reply to the following question from Ryuichi?

>Most likely the rx_pclk fix may be helping your design, as this internal clock was found to be too slow in the earlier configuration, and helped fix an issue at higher temps.
=> Which register's setting will affect above “rx_pclk” ?

Best Regards,
Kanae

Kanae, I just took a brief look at the differences in the two files, and that is the main one that i saw.  The other differences could also be applicable, but just wanted to provide my opinion.  The value is in PHY_1371 as mentioned earlier.

Regards,

James