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AM2634: AM2634 M4 core(HSM) with external flash

?? ?
Prodigy 65 points
Part Number: AM2634

Tool/software:

If R5F core and M4 core all need to access external flash to read data, how to ensure that the external flash is accessed only by one core at a time? I'm currently have a problem. The R5F app program will access and write to the external flash, and the M4 core also needs to read from the flash. There are occasional cases where the data read by the M4 core is incorrect. It is unknown whether this is caused by simultaneous access by both cores. M4 core read external flash data by memcpy Function.


  • 0
    TI__Guru* 84926 points

    Hi,

    May I know which core is owning the configuration of the flash? 

    The memcpy from flash requires flash to be configured in DAC mode, whereas the writing to the flash should be done with INDAC mode. 
    So, may I know if this is considered in the above scenario?

    Thanks and Regards,

    Nikhil Dasan

  • 0 in reply to Nikhil Dasan
    Prodigy 65 points

    external flash driver(qspi) init  is in R5F0 core. I only need to read external flash data in M4 core, not writing.

    I don't know the IDAC mode, could you give me more information?

    If I don't consider it, R5F0 and M4 all read external flash data, whether it make read error flash data? Because I didn't consider that R5F0 and M4 would both  read data from the external flash at the same time.

  • 0 in reply to ?? ?
    TI__Guru* 84926 points

    Hi,

    Sorry for the confusion here. 

    Could you help me understand how are you doing memcpy in HSM core? i.e. what is src address and what is destination address?

    Also are you using flash write APIs on the R5F side as well during this process?

    Thanks and Regards,

    Nikhil Dasan

  • 0 in reply to Nikhil Dasan
    TI__Guru* 84926 points

    Additionally, for doing a memory mapped read, please refer the steps mentioned in the API Flash_norQspiRead() in the path C:\ti\mcu_plus_sdk_am263x_10_02_00_13\source\board\flash\qspi\flash_nor_qspi.c

  • 0 in reply to Nikhil Dasan
    Prodigy 65 points

    example:

    uint8 temp[16];

    memcpy(temp, 0x60050000,16);

    copy 16 bytes from external flash(src address:0x60050000) to temp(des address).

    Also are you using flash write APIs on the R5F side as well during this process?

    Answer: maybe, because R5F have autosar CP(OS), so when M4 core deal with R5F request, R5F may do other task(read/write flash) at the same time.Theoretically, this is possible. Currently, memcpy can read error flash data in M4 core Occasionally.

  • 0 in reply to ?? ?
    TI__Guru* 84926 points

    Hi,

    As you see in the block diagram, the QSPI can either be in memmap port or config port, but not both. 

    So, when you are setting the QSPI to be in memmap port in M4 to read from address and the R5 writes or commands sent on R5 side will set the QSPI to config port, which would lead to non-availability or error data when read using memmap at this point.

    Hence, In such cases, care should be taken that there are no write or command operations on r5 while the data is being read from HSM core.

    Else, a better approach would be to keep only one master for QSPI who would read and write (i.e. R5) and sends data to HSM using IPC or any other approach.

    Thanks and Regards,

    Nikhil Dasan