Original question:
Tool/software:
Hi, Gundavarapu
I have several questions about the ecc functionality of flash.
1. flash ecc is an error correction mechanism for flash data inversion, are spi ecc, sci ecc is the same?
2. flash ecc can be tested by the following method, which describes the CPU error handler can catch the error, could you please explain how to know ECC error occurs? Only by reading the FEDAC_GBLSTATUS register?
3. When an ECC error occurs, how do you know where it occurred?
Hi Sam,
1. flash ecc is an error correction mechanism for flash data inversion, are spi ecc, sci ecc is the same?
No, they are not the same.
Flash ECC is applicable for all the flash memory available in the controller.
As you can see there is 4MB flash in the device right, so this 4MB flash will has its corresponding ECC memory to store the ECC of the written data. And this ECC will act as verification bits for your data. That means if any corruption occurs in the data, then we will get events.
Whereas SPI ECC or SCI ECC is specific to the corresponding peripheral.
For example, if you verify MibSPI there will be a RAM to store the data received or data to be transmitted right, so this memory will also have ECC validation.
2. flash ecc can be tested by the following method, which describes the CPU error handler can catch the error, could you please explain how to know ECC error occurs? Only by reading the FEDAC_GBLSTATUS register?
Not only registers, you will also get ESM events for flash errors based on type of the error.
For Correctable errors in flash you will get ESM 1.4:
For Uncorrectable errors you will get ESM2.3 or ESM3.13
You can download our diagnostic library from below link:
SAFETI_DIAG_LIB Driver or library | TI.com
In this diagnostic library you can find example codes for all the diagnostics in the device.
For flash related diagnostics, you can find with below API name:
SL_SelfTest_Flash
3. When an ECC error occurs, how do you know where it occurred?
EPC module will help to capture the address of the ECC errors. Please refer this chapter once for more details.
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Thanks & regards,
Jagadish.
Hi，jundavarapu
My goal is to test the functionality of FLASH ECC. If a single-bit error or double-bit error occurs, I want to know where it happened and then record it (single-bit errors need to be counted).
First, I need to simulate FLASH ECC errors. Based on your reply in another forum, I downloaded your FEE_ECC_Errors_TEST_LC4357.zip project.
I have some questions about this project that I don't quite understand.
-------------------------------------------- TEST DIAGMODE = 7------------------------------------------
As shown in the figure below, I executed the code at the horizontal line in the figure.
Since mode 7 is used, as expected, PortAErrStat should not be 0, the ESM Stat1 register should not be 0, Group1_Error should be set, and the ERROR light should not be on, but the result is the opposite, as shown in the figure below.
Can you explain what this phenomenon is all about?
Also, what are the concepts of PoartA and PoartB in the figure below?
What problems will arise if the ECC error interrupt for Port B cannot be triggered?
---------------------------------------------TEST DIAGMODE = 5----------------------------------------------
Perform the self-test shown in the figure below.
The results are shown below.
The selected register states are all as expected, but I noticed that regardless of whether the parameter passed is FLASH_ECC_TEST_MODE_1BIT or FLASH_ECC_TEST_MODE_2BIT, the Group2Error variable is set. Why is the Group1Error variable not set when the parameter passed is FLASH_ECC_TEST_MODE_1BIT?
In mode 5 diagnostic mode, is the address tag error in Group3 always triggered?
Hi Sam,
I think you downloaded the code from below link right:
Did you download this code only?
If yes, then as mentioned in this comment this code is only working for port-A. So, can you please try for port-A first?
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Thanks & regards,
Jagadish.
