• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 31 subscribers
  • Views 244 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM263P4-Q1: TRM Clarification on OSPI

Dylan Kwong
Prodigy 90 points

Part Number: AM263P4-Q1
Other Parts Discussed in Thread: ADS127L18

Tool/software:

Hello, 

Could I get some clarification on the follow questions? Mainly:

1. I'm seeing conflicting tables of the clocking pins used in OSPI. The datasheet says there are 4 pins (CLK, CLKLB, LBCLKO and DQS) while the TRM and everywhere else I look only acknowledges 3 (CLK, LBCLKO and DQS)

2. What are the differences between the 4 clocking topologies mentioned in the paragraph below? Also, in the last 2 sentences, it says Internal Pad Loopback can't be used for either SDR and DDR transfers. Is this accurate or a typo? 

3. This is a bit less concrete, but could OSPI be used to interface with a different communication protocol (eg not an OSPI Flash chip)? Specifically, we are looking at the viability of interfacing OSPI with an ADS127L18 ADC which uses an FSDP output port. This consists of purely outputs, including 8 data lines, a clock, and a frame sync. Thus our proposal is connecting the data lanes, the FSDP clock to the OSPI receive clock and the frame sync to a GPIO. Would this be possible?

Thank you, 

Dylan

  • 0
    TI__Expert 4350 points

    Hi Dylan,

    Thank you for your query.

    Please allow us to get back on this by early next week.

    Thanks & Regards,
    Rijohn

  • +1 in reply to Rijohn Pius
    TI__Expert 4350 points

    Hi Dylan,

    Thank you for your patience!!


    The above image is the logical block diagram for the clocking topologies.


    Dylan Kwong said:
    The datasheet says there are 4 pins (CLK, CLKLB, LBCLKO and DQS) while the TRM and everywhere else I look only acknowledges 3 (CLK, LBCLKO and DQS)

    Yes, CLKLB is present as seen in the image loops back inside. It does not come out as a BALL PIN (as marked with LB). ie, it is not used/given for any external peripheral clocking logic.

    Four Clocking Topologies with PHY enabled

    1. Internal phy loopback: Adapted loopback clock is disabled. DQS is disabled. ref_clk is driven into RX_DLL for sampling read data.
    2. Internal pad loopback: Adaptive loopback clock is enabled. DQS is disabled. Loopback clock (OSPI_CLKLB) is driven into RX_DLL through ospi_iclk using OSPI_CONFIG_ICLK_SEL = 1.
    3. External board loopback:  Adaptive loopback clock is enabled. DQS is disabled. Loopback clock (delayed OSPI_LBCLK) is driven into RX_DLL through ospi_iclk using OSPI_CONFIG_ICLK_SEL = 0
    4. DQS: DQS enable has priority over adaptive loopback clock. Data strobe signal from external flash memory, is connected to the OSPI_DQS pin of the SOC. DQS is driven into RX_DLL.

    The LB clk sel mux is implemented as bit field in MSS_CTRL_OSPI_CONFIG.OSPI_CONFIG_ICLK_SEL

    Dylan Kwong said:
    it says Internal Pad Loopback can't be used for either SDR and DDR transfers. Is this accurate or a typo? 

    This is a typo. It supports both SDR and DDR in AM263Px.


    Dylan Kwong said:
    This is a bit less concrete, but could OSPI be used to interface with a different communication protocol (eg not an OSPI Flash chip)? Specifically, we are looking at the viability of interfacing OSPI with an ADS127L18 ADC which uses an FSDP output port. This consists of purely outputs, including 8 data lines, a clock, and a frame sync. Thus our proposal is connecting the data lanes, the FSDP clock to the OSPI receive clock and the frame sync to a GPIO. Would this be possible?

    This is not supported.


    Thanks & Regards,
    Rijohn