Tool/software:
In USB device IN transfer, DMA transfer completion to FIFO can be detected by IOC or ISP interrupt, but is there a way to detect when transmission from FIFO to USB bus is complete?
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Tool/software:
In USB device IN transfer, DMA transfer completion to FIFO can be detected by IOC or ISP interrupt, but is there a way to detect when transmission from FIFO to USB bus is complete?
Hi Motofumi,
but is there a way to detect when transmission from FIFO to USB bus is complete?
By above do you mean that the actual time when the USB data is transferred via USB data bus?
Regards,
Tushar
Hi Tushar,
Thank you for your reply.
By above do you mean that the actual time when the USB data is transferred via USB data bus?
Yes, I do.
best regards,
Motofumi
Hi Motofumi,
Yes, I do.
You can monitor the channelTrigger function which set the DRBL register to initiate data transfer. Once the DRBL register is set, the data is transferred on the bus.
Regards,
Tushar
Hi Tushar,
Thank you for the information.
In the sample project I am looking at (cdc_echo_freertos_am243x-evm_r5fss0-0_freertos_ti-arm-clang), there is no access to the DRBL register in the channelTrigger function.
Which sample should I refer to?
best regards,
Motofumi
Hi Motofumi,
Sorry, for the confusion. I checked the code and it sets the EP_CMD register bits (DRDY and ERDY) to ring the dorbell.
Regards,
Tushar
Hi Tushar,
Thank you for your reply.
I have already confirmed that writing to EP_CMD is implemented in the sample and that it works.
When writing to the EP_CMD register bits (DRDY and ERDY), if the host side has not issued an IN transfer request, I believe that no packets will be sent to the USB data bus.
In that case, is there a way to detect when an IN transfer request has arrived?
This refers to a situation where DMA transfer has already been completed and the system is waiting for an IN transfer request, such as the transmission of a null packet or short packet.
Hi Motofumi,
You can read the EP_ISTS register for this details. The EP_ISTS[4] DESCMIS bit will be set and an interrupt will be generated if device is requested to send data to host and none of Transfer Descriptor is prepared [IN transfer].
Regards,
Tushar
Hi Tushar,
This issue has been resolved. Thank you very much.
I have created a separate thread for another issue, so I would appreciate it if you could take a look at that as well.
best regards,
Motofumi
Hi Motofumi,
Thanks for the confirmation. Closing this thread.
so I would appreciate it if you could take a look at that as well.
Sure.
Regards,
Tushar