MSPM0L1306: The generated.txt file has two addresses.

Kitto Chen

Part Number: MSPM0L1306

Tool/software:

Why does the.txt file generated when compiling the MSPM0 code have two addresses? Two addresses will affect the CRC check result of the upgrade package. How to set the CCS so that the.txt file generated by compilation has only one address?

9 months ago

0 Janz Bai 9 months ago

TI__Genius 13270 points

Hello Kitto,

Please check whether you set two Flash region in your code or in your configuration. For example, you write one part code from 0x0, and write another part code to region starting from 0x2140. Otherwise, you won't get this kind of ti txt file.

And to double confirm, you can check the device_linker.cmd file to see the memory region configuration,

And please confirm you generate the ti txt file in correct method: properties -> Arm Hex utility -> Enable " Arm Hex Utility" -> "--drag_wrap=off". Then click "Output Format Options" -> choose ti txt

You can find one SDK demo to test, you may find you can get a normal ti txt file.

Best Regards,

Janz

0 Kitto Chen 9 months ago in reply to Janz Bai

Prodigy 20 points

My Settings should be correct, but it will probabilistically generate a.txt file containing two addresses. What else could be the reasons for this?

0 Janz Bai 9 months ago in reply to Kitto Chen

TI__Genius 13270 points

Hello Kitto,

It seems very strange. In your app code, do you have any action such as, write some part code to any fixed address in Flash? And please try to import one SDK demo code and generate the txt file through the same method, and check whether the file is normal.

Best Regards,

Janz

0 Kitto Chen 9 months ago in reply to Janz Bai

Prodigy 20 points

1. The example of the SDK selects to output txt, and the compilation will not generate a txt containing two addresses.
2. I didn't write the code with the specified address in flash. Only when the size of the code is within a certain range will the compilation generate two addresses. For example, after deleting or adding code, no two addresses will be generated again. Are there any setting options that optimize the generated TXT file?

0 Dennis Lehman 9 months ago in reply to Kitto Chen

TI__Guru 71216 points

Hi Kitto,

Based on the device_linker.cmd file you show above, the FLASH length is set incorrectly. It should be 0x0000FFF8.

0 Kitto Chen 9 months ago in reply to Dennis Lehman

Prodigy 20 points

Thank you for your reply.
1. The FLASH_SIZE is used to limit the size of this bootloader. Even after being modified to 0x0000FFF8, two addresses will still be generated.
2. FILL=0XFFFFFFFF can solve the problem of generating two addresses, but the unused address at the end is also filled. Can only the unused address in the middle be filled?

0 Janz Bai 9 months ago in reply to Kitto Chen

TI__Genius 13270 points

Hello Kitto,

Could you send your project to us here, and we can check it on our side,

best Regards,

Janz Bai

0 Dennis Lehman 9 months ago in reply to Kitto Chen

TI__Guru 71216 points

Ok, so it appears you are using a "secondary" FLASH BSL rather than using the ROM BSL included in the device, correct?

If so, then your BSL resides in locations 0x0000.0000 - 0x0000.2C00, and the remaining portion of FLASH is reserved for the application, correct?

Referring to the SDK example "secondary_bsl_uart_LP_MSPM0L1306_nortos_ticlang", if you modify this linker script file as shown below, the *.txt output file will have all unused FLASH locations filled with 0xFFFFFFFF (see attached .txt file)

MEMORY
{
	FLASH_SBSL_INTVEC(RWX)  :	 org = 0x00001000,      len = 0x00000040, FILL = 0xFFFFFFFF
	FLASH_SBSL_START(RWX)   :	 org = 0x00001040,      len = 0x00000040, FILL = 0xFFFFFFFF
	FLASH_SBSL(RWX)   		:	 org = 0x00001080,      len = 0x00001F80, FILL = 0xFFFFFFFF

    SRAM(RW)				:    org = 0x20000000,      len = 0x00001000,

    BCR_CFG		 		    : 	 org = 0x41C00000,      len = 0x00000080,
    BSL_CFG				    : 	 org = 0x41C00100,      len = 0x00000080,
    FACTORY_CFG		  		: 	 org = 0x41C40000,      len = 0x00000200,
}

Fullscreen secondary_bsl_uart_LP_MSPM0L1306_nortos_ticlang.txt Download

@1000
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11 70 00 F0 C1 F8 B0 BD 00 20 A5 21 F7 E7 C0 46 
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00 26 0F 4F 60 88 86 42 17 D2 28 46 08 38 01 68 
28 1F 03 68 2A 68 00 2A 03 D0 18 46 00 F0 EA F9 
08 E0 06 48 87 42 05 D0 48 1C 09 78 89 00 7A 58 
19 46 90 47 76 1C 0C 35 E4 E7 F8 BD C8 23 00 00 
BC 23 00 00 70 B5 0D 48 40 1C 02 D0 0B 48 FF F7 
D3 FF 0B 48 0B 4C 84 42 0C D0 0B 4D 0B 4E B5 42 
08 D0 2A 68 69 68 50 1C 12 78 92 00 A2 58 90 47 
08 35 F4 E7 00 BF 00 BF 70 BD C0 46 68 10 00 00 
C8 23 00 00 BC 23 00 00 E0 23 00 00 00 24 00 00 
70 B5 11 22 13 02 C2 18 C4 58 01 25 AC 43 C4 50 
0C 88 8D 78 25 43 8C 88 2C 43 C5 58 08 4E 2E 40 
08 4D 25 40 74 19 C4 50 88 79 CB 79 03 43 08 7A 
18 43 51 68 7E 23 99 43 18 40 08 18 50 60 70 BD 
E7 98 FD FF 18 67 00 00 1C B5 0A 00 17 D0 00 23 
01 24 E4 07 A0 42 00 D2 04 00 94 42 01 D9 52 00 
FB E7 90 42 5B 41 90 42 00 D3 80 1A 91 42 01 D2 
52 08 F6 E7 19 00 02 00 08 00 11 00 1C BD 01 00 
00 20 00 F0 60 F9 1C BD 80 B5 0B 49 0A 68 08 23 
13 70 0A 68 02 23 53 70 0A 68 00 23 93 70 0A 68 
3B 23 D3 70 0A 68 10 71 04 48 00 68 C3 68 05 21 
10 46 98 47 80 BD C0 46 F0 00 00 20 F4 00 00 20 
B0 B5 0A 48 00 78 A5 28 0C D1 09 4D 00 24 2C 60 
08 48 FF F7 D9 FA 00 28 01 D1 0D 20 C4 43 07 20 
28 60 00 E0 01 24 E0 B2 B0 BD C0 46 00 01 00 20 
00 13 40 40 00 D0 0C 40 B0 B5 0B 48 01 22 51 04 
0A 4B 1C 68 95 02 AC 43 1C 60 5C 68 12 05 94 43 
5C 60 02 68 0A 42 05 D0 02 68 0A 42 02 D0 02 68 
0A 42 F6 D1 B0 BD C0 46 04 02 0B 40 00 01 0B 40 
10 B5 04 46 FF F7 A8 FA 03 28 0C D1 06 48 20 18 
06 49 61 18 00 22 02 60 42 20 08 60 04 48 C8 61 
20 46 FF F7 F9 FA 10 BD 10 12 00 00 04 11 00 00 
00 00 C0 41 80 B5 07 48 07 49 01 60 0F 20 00 F0 
C5 F8 01 20 C1 03 05 4A 11 60 BF F3 4F 8F BF F3 
6F 8F 80 BD 04 88 10 40 03 00 00 B1 80 E1 00 E0 
05 48 06 49 41 60 06 49 01 60 01 68 C9 07 FC D0 
04 48 02 21 01 60 70 47 00 08 44 40 03 00 00 B1 
01 00 00 26 00 11 44 40 08 48 80 F3 08 88 00 BF 
00 BF 00 F0 D8 F8 00 28 01 D0 FF F7 F3 FE 00 20 
FF F7 C2 FA 01 20 00 F0 C9 F8 C0 46 FC 0F 00 20 
06 4A 00 23 DB 43 13 60 00 29 04 D0 03 78 13 71 
49 1E 40 1C F8 E7 90 68 70 47 C0 46 04 11 44 40 
06 4A 00 23 DB 43 13 60 00 29 04 D0 03 78 13 71 
49 1E 40 1C F8 E7 90 68 70 47 C0 46 04 11 44 40 
04 49 01 22 12 03 8A 61 03 4B 18 60 08 68 10 42 
FC D0 70 47 30 90 10 40 20 91 10 40 80 B5 FF F7 
6D FE FF F7 A5 FF FF F7 A9 FC 02 48 02 21 01 60 
80 BD C0 46 B0 E3 0C 40 10 B5 01 22 12 03 83 18 
0C 78 9C 60 4B 78 83 50 89 78 01 4A 81 50 10 BD 
0C 11 00 00 10 B5 04 4A 83 18 06 24 84 50 D9 61 
FF F7 62 FA 10 BD C0 46 04 11 00 00 B0 B5 04 4B 
C4 18 02 25 15 43 C5 50 E1 61 FF F7 55 FA B0 BD 
04 11 00 00 04 48 01 68 C9 07 FC D0 00 68 02 21 
01 40 48 08 70 47 C0 46 D0 E3 0C 40 03 22 80 58 
00 28 05 D0 40 1E 4A 1C 00 23 0B 70 11 46 F7 E7 
70 47 FE E7 03 48 40 8B 80 05 00 0B 01 21 49 07 
40 18 70 47 00 00 C4 41 02 48 03 21 01 60 02 49 
41 60 FE E7 00 03 0B 40 01 00 00 E4 80 00 02 49 
40 18 02 49 01 64 70 47 00 00 00 20 03 23 00 00 
10 B5 01 22 12 03 83 18 0C 78 9C 60 49 78 81 50 
10 BD 10 B5 00 23 9A 42 03 D0 CC 5C C4 54 5B 1C 
F9 E7 10 BD 80 B5 0B 46 03 21 42 58 C1 1D 18 46 
00 F0 10 F8 80 BD 70 47 02 48 00 8B 00 05 80 0A 
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0 Kitto Chen 9 months ago in reply to Janz Bai

Prodigy 20 points

Hi Janz,
Please help check this debugging code. In the code of our other TI projects, two addresses will also be generated occasionally after the code size is changed, not just in this debug code.
mspm0l1306_bootloader.zip

0 Janz Bai 9 months ago in reply to Kitto Chen

TI__Genius 13270 points

Hello Kitto,

I have checked your code. And I found the send part seems like the vector table format. Then I delete the SCB->VTOR = app_addr from the code, then I found that there won't be second address. So I suspect that this code "SCB->VTOR = app_addr " which is operate the address of vector table cause generating two address, I think complier do something when build this code.

And I want to know whether customer concern about that there are two address, I think it won't affect customer app code function.

Best Regards,

Janz Bai

0 Kitto Chen 9 months ago in reply to Janz Bai

Prodigy 20 points

Hi Janz,
Delete the SCB->VTOR = app_addr and change the array length from 256 to 512, the second address will also appear.

This will affect the CRC check function because after writing txt to Flash, the blank part will be filled with 0xFF, resulting in inconsistent CRC check results calculated for txt and those calculated for flash.

+1 Dennis Lehman 9 months ago in reply to Kitto Chen

TI__Guru 71216 points

Hi Kitto,

Take a look at the project's *.map file. There is a lot of information that can help track down what/why you see in your output file.

For example, looking at .map file, it appears the end of the BSL is 0x00002114 in the .text section and your program's consts are placed in the .ro memory section at 0x00002120.

When I don't have SCB->VTOR commented out, you see the BSL ends at 0x00002114 and the .ro memory section is placed at 0x00002120.

When I do comment out the SCB->VTOR, and yes the addresses are slightly different, but you can see the .ro memory section follows the .text section and is placed at 0x00002140 and this is the address that does still appear in the .txt file.

Do you see this too?

Arm-based microcontrollers

Arm-based microcontrollers forum

MSPM0L1306: The generated.txt file has two addresses.