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TMS570LC4357: MIbSPI and MII

Veena Saluja
Prodigy 130 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Tool/software:

Hi - on tms570 HDK, we want to use  one one HDK ( example HDK1) to do  MibSPI comms with 4 other HDKs using MibSPI1,2, 3 and 5 as there is no MIb SPI available for channel 4. We want to also use MII for Ethernet comm with another device on HDK1. But Pin MUX in Halcogen, seems to have a conflict on G19 and R2 for MII and MibSPI thereby limiting to  only two MibSPI channels ( 2 and 3) being available with MII. Although Halcogen shows U3 as default Option for MII, it is not available on the HDK? Is there another workaround/fix for this limitation?

  • 0
    TI__Guru 73781 points

    Hi Veena,

    Apologies for the delayed response.

    What makes you to think MibSPI doesn't support on channel-4.

    I could see all 5 insteances have MibSPI provision:

    As you can see MibSPI pins are also available for MibSPI4:

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 130 points

    Hi Jagdish,

    Thanks for the response. You are correct we can use MibSPI4. We are still limited to three channels : MibSPI2, MibSPI3 and MIBSPI4. We can't use MibSPI1 and MibSPI5 with MII enabled. Is there any workaround so that we can use 4 MIBSPI channels with MII?

  • 0 in reply to Veena Saluja
    TI__Guru 73781 points

    Hi Veena,

    Apologies for the delayed response, i was off for few days due to some personal work.

    Only MibSPI5 has issue and remaining MibSPI's will work without any issues.

    These two MibSPI1 pins are not required for normal MibSPI communication.

    They needed for only parallel communication, i mean for sending data on two or more lines. For normal MibSPI communication MIBSPI1SOMI[0] and MIBSPI1SIMO[0] are just sufficient.

    Regarding MibSPI5 we need to compromise with MII, i mean only we can choose one of them.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 130 points

    Hi Jagdish,

    Thanks for looking into. If we use MIBSPI1 with Enable and Chip Select 0 we get a conflict in Halcogen with MII on G19 (MIBSPI1nENA and MII_RXD[2] for and R2 ( MIBSPI1NCS[0] and MII_TXD[2] pins?

  • 0 in reply to Veena Saluja
    TI__Guru 73781 points

    Hi Veena,

    Regarding chip select:

    We no need to use CS0 for communication we have flexibility to use any one of the eight CS lines.

    So, i hope CS is not problem in your case.

    Regarding ENA, enable is not a mandatory line in mibSPI communication. It is helpful for slave to delay the clock generation from Master.

    Many customers will not use this signal. You might need this signal in high throughput cases, where slave need some processing time between the frames.

    If you really need this line, then we might not use MibSPI1 also in your application.

    --
    Thanks & regards,
    Jagadish.