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MSPM0G1519: comparator event generation with blanking

Munan Xu
Expert 4940 points
Part Number: MSPM0G1519

Tool/software:

Hello,

I have a customer who's trying to implement comparator blanking on the MSPM0G1519 and they're running into a weird issue where it seems like events are not triggering based on the output of the comparator when the blanking source is active.

Based on the diagram in the TRM it would appear that a comparator event would trigger an event regardless of the status of BLANKSRC. 

However the customer finds that through mapping the comparator falling edge event to a GPIO, they are not seeing the GPIO toggle until after the blanking source is cleared.

Any insight on why that may be the case?

Munan

  • 0
    TI__Expert 3440 points

    Let me check it and reply to you later.

    Best Regards,
    Peter Jiang

  • 0 in reply to Peter Jiang
    TI__Expert 4940 points

    Hi Peter,

    I had a chance to do a little bench testing on my side. I set up a comparator with the positive reference going to a pin on the launchpad and internal DAC voltage reference for the negative terminal and enabled the comp output.

    I set up timerA0 to output two pwm channels, one as an input "signal" and one as the blanking source for the comparator.

    I connected the timer output CC1 to the positive input of the comparator and set up both an interrupt and event based GPIO toggle and monitored all the signals:

    So it does appear that the events and interrupts respect the blanking source rather than firing when the comparator would otherwise be high.

    Munan

  • 0 in reply to Munan Xu
    TI__Expert 3440 points

    Hi Munan,

    Much thanks for the efforts to do the test, will reply to you by tomorrow.

    Best Regards,
    Peter

  • 0 in reply to Peter Jiang
    TI__Expert 3440 points

    Hi Munan,

    According to the description of the TRM Comparator Interrupt section as shown below, the interrupt is generated based on the rising and falling edges of the output. Since the Blanking source is enabled, the output is affected, so that also affect the time of interrupt generation. I believe the bench test result form your side is normal and is consistent with the TRM description. Correct me if I misunderstand your question. Thanks!

    Best Regards,
    Peter

  • 0 in reply to Peter Jiang
    TI__Expert 4940 points

    Hey Peter,

    OK that's fine, but then the diagram needs to be updated in the TRM to reflect that.

    Munan