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TMS570LC4357: ECC errors in Release build but not in Debug build

Prajwal T R
Prodigy 10 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Tool/software:

Using Auto ECC generation from CCS while programming in both Debug and Release builds. default .cmd linker file from halcogen.

In Debug session on a debug build, i can see all the CAM entries are available. Error Pin Key status is 0x1H indicating no errors.
Debug ECC Errors

In Debug session on a release build, i can see 2 CAM entries are occupied, Error Pin Key status is 0x0H indicating errors on ECC validation.

CAM entries.

Questions are as follows:

1. How is this behavior different from Debug and Release builds ?
2. `The write data is masked with byten and stored into CAM on each index.` of 12.4.9 CAM Content Update Register n (CAM_CONTENT), i am having trouble comprehending what this statement means.

Thanks in advance

  • 0 in reply to Prajwal T R
    TI__Guru 70171 points

    Hi Prajwal,

    Prajwal T R said:
    1. How is this behavior different from Debug and Release builds ?

    Usually release mode build has higher optimization levels whereas debug mode has no optimizations.

    Prajwal T R said:
    `The write data is masked with byten and stored into CAM on each index.` of 12.4.9 CAM Content Update Register n (CAM_CONTENT), i am having trouble comprehending what this statement means.

    I will check this out.

    --
    Thanks & Regards,
    Jagadish.

  • +1 in reply to jagadish gundavarapu
    Prodigy 10 points

    Hi Jagadish, 

    I had some success in getting accurate ECC values to be populated at designated Flash ECC space 0xF0400000 by modifying .cmd file and Enabling --ecc=on option in linker (CCS) (This second step is missing from all the guides that talk about Linker generated ECC, This should be updated where necessary by TI team). 

     i get the idea behind storing 64bit aligned address of the flash that generated the fault, regarding the data is masked with byten,still do not understand what it means. any luck ?

    Also i have attached my working .cmd file for reference for anyone interested.


    Thank you, 
    Prajwal T R

    MEMORY
{
/* USER CODE BEGIN (2) */
/* USER CODE END */
    VECTORS (X)  : origin=0x00000000 length=0x00000020 vfill=0xFFFFFFFF
    FLASH0  (RX) : origin=0x00000020 length=0x001FFFE0 vfill=0xFFFFFFFF
    FLASH1  (RX) : origin=0x00200000 length=0x00200000 vfill=0xFFFFFFFF
    STACKS  (RW) : origin=0x08000000 length=0x00001500
    RAM     (RW) : origin=0x08001500 length=0x0007EB00

/* USER CODE BEGIN (3) */
    ECC_VEC  (R) : origin=(0xf0400000 + (start(VECTORS) >> 3))
                   length=(size(VECTORS) >> 3)
                   ECC={algorithm=algoL2R5F021, input_range=VECTORS}

    ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0)  >> 3))
                   length=(size(FLASH0)  >> 3)
                   ECC={algorithm=algoL2R5F021, input_range=FLASH0 }

    ECC_FLA1 (R) : origin=(0xf0400000 + (start(FLASH1)  >> 3))
                   length=(size(FLASH1)  >> 3)
                   ECC={algorithm=algoL2R5F021, input_range=FLASH1 }

/* USER CODE END */
}

/* USER CODE BEGIN (4) */
ECC
{
    algoL2R5F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */
                   hamming_mask = R4         /* Use R4/R5 build in Mask */
                   parity_mask  = 0x0c       /* Set which ECC bits are Even and Odd parity */
                   mirroring    = F021       /* RM57Lx and TMS570LCx are build in F021 */
}
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */

SECTIONS
{
/* USER CODE BEGIN (5) */
/* USER CODE END */
    .intvecs : {} > VECTORS
    .text   palign(8) : {} > FLASH0 | FLASH1
    .const  palign(8) : {} > FLASH0 | FLASH1
    .cinit  palign(8) : {} > FLASH0 | FLASH1
    .pinit  palign(8) : {} > FLASH0 | FLASH1
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM
	

/* USER CODE BEGIN (6) */
/* USER CODE END */
}