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MCU-PLUS-SDK-AM273X: What is the highest rate of CS signal of MSS_SPIB with 4-pin mode for AM273x chipset?

Part Number: MCU-PLUS-SDK-AM273X


Tool/software:

Hello Support team,

We are using AM273x to collect data from AD7389-4 ADC chipset via SPI. Now we find that the sampling rate of the input data is limited by the rate of CS of SPI from AM273x. As shown in the following screenshot, the SPI clock is 20MHz, 4-pin mode, with CS hold enabled, the CS signal period is 14.25 us, so we get the sampling rate 70.2 KHz

Is there any way to increase the CS rate? What's the limit of the CS rate?

My data collection source code is as attached. Could you please check it out if I did something wrong? Or did I make any extra delay between each SPI transaction?

void AD738x_dataConversion(void)
{
    int16_t adcResults[NUM_CHANNELS];
    int32_t transferOK;
    uint8_t txBuf[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
    uint8_t rxBuf[8] = { 0 };
    MIBSPI_Transaction spiTransaction;

    spiTransaction.count            = 8;         // 4 channels x 16 bits = 8 bytes
    spiTransaction.txBuf            = (void *)txBuf;
    spiTransaction.rxBuf            = (void *)rxBuf;
    spiTransaction.peripheralIndex  = 0U;
    spiTransaction.arg              = NULL;

    DebugP_log("Starting AD738x data conversion loop...\n");

    for (int i = 0; i < NUM_SAMPLES; i++)
    {
        // data conversion, first read commands
        transferOK = MIBSPI_transfer(gMibspiHandle[MSS_SPIB_J16], &spiTransaction);
        if ((transferOK != SystemP_SUCCESS) || (spiTransaction.status != MIBSPI_TRANSFER_COMPLETED))
        {
            DebugP_log("AD738x SPI data conversion first read failed!\r\n");
            DebugP_assert(FALSE);
            return;
        }

        // Parse channels from received buffer
        adcResults[0] = ((int16_t)rxBuf[0] << 8) | rxBuf[1];  // Ch1
        adcResults[1] = ((int16_t)rxBuf[2] << 8) | rxBuf[3];  // Ch2
        adcResults[2] = ((int16_t)rxBuf[4] << 8) | rxBuf[5];  // Ch3
        adcResults[3] = ((int16_t)rxBuf[6] << 8) | rxBuf[7];  // Ch4

        // Store results in adcBuffer
        for (int ch = 0; ch < NUM_CHANNELS; ch++)
        {
            adcBufferRaw[i][ch] = adcResults[ch];
        }
    }

    for (int i = 0; i < NUM_SAMPLES; i++)
    {
        DebugP_log("%4d\n", adcBufferRaw[i][0]);
    }

    DebugP_log("Finished data conversion loop, stored %d samples.\n", NUM_SAMPLES);
}

Also for more information, I attached a Saleae capture file for your reference. (please rename it from xxx.txt to xxx.sal)

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Thank you very much for your help and support.

Looking forward to your response.

Best regards,

Lin

  • Hi Lin,

    From the Saleae capture, it seems the data transfer takes about 3.5us for 8 byte data, 5.6us CS low but not clock, and 4.7us CS high. In theory the data transfer rate can be 4 times of the current transfer rate. From the program you shared, I assume you are using the blocking mode. Are you using DMA mode? Are you using the Release build or the Debug build? Can you share your example.syscfg file and the linker.cmd file and the map  file?

    Best regards,

    Ming

  • Hi Ming,

    Yes, I use the blocking mode and I haven't used DMA as shown below. I use Debug build.

    Here are my example.syscfg and map files. I can't find the linker.cmd file.

    8508.example.zip  mibspi_loopback.Debug.zip

    If you need more information, please let me know.

    Thanks and best regards,

    Lin

      

  • Hi Lin,

    Three things you can try:

    1. Change from Debug build to Release build. It will definitely help especially you are using CPU copy

    2. Enable the DMA

    3. Uncheck the "CS HOLD ENABLE"

    Best regards,

    Ming

  • Hi Ming, 

    Thanks for your instructions.

    I finished all the above tests just now.

    1) Change from debug build to release build indeed increase the CS rate from 69.54 KHz to 91.14 KHz. It's really helpful.

    2) Once I enabled DMA as shown in the below screenshot, I got all zero data and the CS rate reduced to 69.95 KHz. In addition to check the Enable DMA box in the example.syscfg, should I do anything else in the code? This is my first time to enable DMA. 

    3) Once I uncheck the CS HOLD ENABLE box, the CS rate will increase a little bit from 91.14 to 92.63 KHz. However at this time all the readback data are not correct as AD7380-4 chipset requires that CS keeps low while the data conversion period.

    So currently the best result is 91.14 KHz with Release build, no DMA and Enable the CS HOLD. However, 91.14 KHz is far away from our requirement. We need to handle at least 500 KHz signals. 

    We appreciate your further advice and suggestions.

    FYI, I attached the Saleae capture files for each configuration.

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    meta.jsonPK#�

    Thanks and best regards,

    Lin

  • Hi Lin,

    If you want to get to 500Khz sampling rate at least, then it is mission impossible with AM273x. Each sample takes 64 bits (4 channel * 16 bit). 500Khz*64 = 32Mhz, but the MIBSPI runs 25Mhz max. You will need to find another device.

    Best regards,

    Ming

  • Hi Ming,

    Totally agree with your calculation and explanation. We have following thoughts.

    One method is to use two SPI to support AD7380-4's 2-wire mode to achieve the target. So we want to further increase the CS rate of MIBSPI to the  theoretical value. If the DMA and the other way can further improve it, we would like to continue the investment.

    Another method (as I asked in previous post) is trying to use the QSPI of AM273x to support ADC's 4-wire mode. If you could provide more advice for the QSPI usage, that would be greatly helpful for our development.

    As we have spent much time on the AM273x chipset, we really hope we can use it to meet our requirement.

    Appreciate your help and support.

    Best regards,

    Lin

  • Hi Lin,

    The idea to use two SPI to support 2-wire mode of the ADC chip is hard to implement in my opinion, because the clock synchronization between two SPI instances is hard to do.

    Using QSPI to support 4-wire mode of the ADC chip is more feasible in my opinion, but it also has its own challenges:

    1. All QSPI examples are tightly coupled with the Flash. Even though there is a QSPI HLD (high level driver) and SPI LLD (low level driver) APIs, but there are no stand alone examples for the QSPI drivers

    2. We do not know the QSPI driver support the mode (Mode 0/1/2/3 etc.) for the ADC chip or not

    3. The support we can provide is limited, because the MCU+ SDK only officially support the QSPI for flash.

    If you go this route, you are on your own.

    If you decided to go this way, then please file another e2e thread for the QSPI driver. There will be a different person to support you from there.

    Best regards,

    Ming 

  • Hi Ming,

    Thank you so much for your quick response.

    We just had an internal discussion and found out it is very hard to use multiple SPI to support ADC's 2-wire or 4-wire mode. You mentioned clock sync issue, we thought  that even the CS sync is an issue. So we will give up that idea.

    For the QSPI, I checked the sample codes before and noticed that they are all closely related to the Flash. As you emphasized that there is no stand alone sample code of QSPI, when we make the final decision, we will take it into account. Thanks for your honesty about limited QSPI support. If we will go that way, we will try our best to figure it out. And definitely I will create another thread for the QSPI if we will do.

    Appreciate your help and support.

    I can close this thread if you don't have any other suggestions

    Best regards,

    Lin

  • Hi Lin,

    I have no more suggestion on MIBSPI side. Please close this thread.

    Best regards,

    Ming

  • Hi Ming,

    Thanks again for your continuous and informative support.

    Best regards,

    Lin