AM2612-Q1: CAN MCAL related question

Part Number: AM2612-Q1

Tool/software:

Hi experts,

I ask this for my customer.

My customer is doing the OTA stress test, and they find CAN communication will have issue in 5min ~ 2 hour.

When the issue happen, if BSW call the CAN_Write, the function will not return error(also no bus-off), but it can't see the CAN frame in CAN bus, and it no longer trigger the CanIf_TxConfirmation interruption. And in this time the CAN can receive frame.

Then they reset the chip and the function will recover(both receive and send is normal). But after 5min~2hour, this issue will happen again.

MCAL version: MCAL_AM261x_10.02.00

CAN configuration: CANFD mode, arbitration domain speed is 500kbps, data domain speed is 2Mbps, receive and send use interruption mode.

What's any other information that customer need provide to help them to find the root cause?

BRs

Shuqing

  • Hi Shuqing,

    Does Can_Write() return BUS_BUSY?

  • Hi Shuqing,

    Per meeting this morning, please check with Robosense engineers for the resistor termination on CAN bus, and content of MCAN config and status registers. 

    As we mentioned in the meeting, the request pending bit will be reset (cleared to 0) after a requested transmission has completed or has been canceled. after the pending bit is set, the TX message handling will check the pending TX request and start transmission.

    The TXBAR (request) and TXBRP (pending) is set only for the TX buffers configured in TXBC register (start address and number of TX buffers). The request will be ignored if the it is already in pending.

  • The Can_Write() of AM26x MCAL driver does add transmission request (set bit of TXBAR) after message has been written to MSG RAM:

    1. MCAN_writeMsgRam(baseAddr, memType, messageBox, &elem);

    2. MCAN_txBufAddReq(baseAddr, canMessageBox);

  • Hi Qingjun,

    Customer  enable the automatic retransmission, and problem happen again. And they check the CFG_TXBRP register value when the problem happen, it isn't set. 

    I also upload the register value: https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/SaveReg.hex

    Could you help to check if it any abnormal?

    BRs

    Shuqing

  • HI Shuqing,

    I will check the data in SaveReg.hex file.

  • Hi Shuqing,

    Please find my interpretation of the data in SaveReg.hex:

    :20 8200 00 08063832 21436587 00000000 320A8100: DSJW=3, DTSEG2=2,DTSEG1=10, DBRP=1, TDC=1
    80000000 FFFF0000 40030000: ASM=1, DAR=0, FDOE=1, BRSE=1,
    0F2E0108:NTSEG2=15, NTSEG1=0x2E, NBRP=1,SJW=4
    D2
    :20 8220 00 00000E00 00000000 0000FFFF FFFF0000 00000000 00000000 00000000 00000000 34
    :20 8240 00 00000000 08301000(PSR):LEC=00, ACT=1(Idle), DLEC=1 (Stuff error), TDCV=0
    0A060000(TDCR):TDCF=0A, TDCO=06
    00000000
    03000820(IR): RF0N=1, RF0W=1, DRX=1, ARA=1
    09020800(IE): RF0NE=1, RF0LE=1,TCE=1, DRX=1
    00000000 01000000(ILE): Interrupt line 0 is enabled
    87
    :20 8260 000000000000000000000000000000000000000000000000000000000000000000FE
    :20 8280 00 3F000000(GFC): reject remote frames, accept non-matching frames
    00000300(SIDFC):FLSSA=0, LSS=3
    00000000(XIDFC): no
    00000000 FFFFFF1F(XIDAM):
    00000000
    01000000(NDAT1): new data flag is set in RX buffer #1
    00000000 7F
    :20 82A0 00 38010403(RXF0C):F0SA=0138, F0S=4(RX FIFO0 size), F0WM=3(watermark), F0OM=0(blocking mode)
    03010000(RXF0S): F0FL=3, F0G1=01, others=0
    00000000
    E8020000(RXBC): RBSA=0x02E8, RX Buffer
    000000000000000000000000
    07070000 (RXESC)
    82
    :20 82C0 00 18000002(TXBC):TBSA=0018, NDTB=0(dedicated TX buffer), TFQS=2 (# of buffer in TX FIFO/Queue), TFQM=0
    02010100(TXFQS):TFFL=0x12
    07000000(TXESC): 64 bytes data field
    00000000:(TXBRP): TX request pending, TRP=0
    00000000(TXBAR):AR=0, no request
    00000000(TXBCR):CR=0, cancellation request=0
    00000000(TXBTO): TO=0, no transmission occurred
    01000000(TXBCF):CF=0, no cancellation
    78
    :20 82E0 00 03000000(TXBTIE):TIE=03, enabled for TX buffer 1 and buffer 2
    00000000(TXBCIE): TX cancellation interrupt, 0
    00000000
    00000000
    00000A03(TXEFC): EFSA=0x0, EFS==10, EFWM=3
    00000000 00000000 00000000 6E

    From the data, your will see that TX buffer start address is at 0x18, but the TX buffer count is zero. There is no TX pending, and TX request, and no transmission occurred. 

    The ASM bit in CCCR is set which means that the restricted operation mode is used. In restricted operation mode, the CAN node is able to receive data and remote frames and to give acknowledgment to valid frames, but the node does not send data frames, remote frames, active error frames, or overload frames. In case of an error condition or overload condition, the node does not send dominant bits; instead, the node waits for the occurrence of bus idle condition to resynchronize to the CAN communication. The restricted operation mode is automatically entered when the Tx Handler is not able to read data from the Message RAM in time. To leave restricted operation mode, the host CPU has to reset the MCAN_CCCR.ASM bit.