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MSPM0G1507: Flash controller behavior during write

Munan Xu
Expert 4940 points
Part Number: MSPM0G1507

Tool/software:

Hello,

Just wanted to confirm the behavior of the flash module when performing a program/ erase operation. In section 7.2.1 of the TRM it states that all read requests on the same bank would stall until the operation is completed:

But then in section 7.3.1 it states that read access to the same flash bank that's being programmed/ erased can be unpredictable:

It appears what actually happens on device is that read access stalls until after the command completes. Can we confirm that this is what's expected? And if so, can we clarify the second statement in the TRM?

Munan

  • 0
    TI__Mastermind 24265 points

    Hi Munan,

    I also think the TRM description is little confusing.

    I prefer the second statement, as the read behavior is not controlled by flash controller, the flash controller mainly control the write/erase/verify behavior. So, I assume it doesn't have a mechanism to block CPU access.

    We always recommend that when operate the single bank device with flash controller, then make sure the operation is handdle in SRAM (load this partial code into SRAM). When operate dual bank device, it is okay to put all flash controller operation in the flash bank when process the other flash bank.

    B.R.

    Sal

  • 0 in reply to Sal Ye
    TI__Expert 4940 points

    Hey Sal,

    OK thanks for the clarification. For customers who are implementing this flash write command in flash, what's the mechanism that's causing the code to appear to be working correctly? are we just banking on the cache to fully contain the while loop check for the status change?

    Munan

  • 0 in reply to Munan Xu
    TI__Mastermind 24265 points

    Hi Munan,

    Munan Xu said:
    For customers who are implementing this flash write command in flash, what's the mechanism that's causing the code to appear to be working correctly?

    Right now, we have the move this kind of flash operation to RAM (with a while loop to check its status), so that it has independency with flash operation.

    Furthermore, it is better also disable interrupt during flash operation, as interrupt routine is execute in flash if not special put into RAM. - This is not part of SDK solution, but I think it will be safer.

    B.R.

    Sal