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MSPM0G3507: about timer triggering ADC conversion

Part Number: MSPM0G3507
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hello,

I have a project which uses the Timer0 to trigger ADC conversion. The Timer0 period is set as 1.125s while the Timer clock frequency as 3.64KHz.

The event publisher is Timer0 and the event subscriber is ADC12_0. The conversion occurs every 100us. But I couldn't find where 100us is configured in the SysCfg. 

Here is the ADC12_0 init function in ti_msp_dl_config.c:

SYSCONFIG_WEAK void SYSCFG_DL_ADC12_0_init(void)
{
    DL_ADC12_setClockConfig(ADC12_0_INST, (DL_ADC12_ClockConfig *) &gADC12_0ClockConfig);

    DL_ADC12_initSeqSample(ADC12_0_INST,
        DL_ADC12_REPEAT_MODE_ENABLED, DL_ADC12_SAMPLING_SOURCE_AUTO, DL_ADC12_TRIG_SRC_EVENT,
        DL_ADC12_SEQ_START_ADDR_00, DL_ADC12_SEQ_END_ADDR_03, DL_ADC12_SAMP_CONV_RES_12_BIT,
        DL_ADC12_SAMP_CONV_DATA_FORMAT_UNSIGNED);
    DL_ADC12_configConversionMem(ADC12_0_INST, ADC12_0_ADCMEM_2,
        DL_ADC12_INPUT_CHAN_2, DL_ADC12_REFERENCE_VOLTAGE_VDDA, DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP0, DL_ADC12_AVERAGING_MODE_DISABLED,
        DL_ADC12_BURN_OUT_SOURCE_DISABLED, DL_ADC12_TRIGGER_MODE_AUTO_NEXT, DL_ADC12_WINDOWS_COMP_MODE_DISABLED);
    DL_ADC12_configConversionMem(ADC12_0_INST, ADC12_0_ADCMEM_3,
        DL_ADC12_INPUT_CHAN_3, DL_ADC12_REFERENCE_VOLTAGE_VDDA, DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP0, DL_ADC12_AVERAGING_MODE_DISABLED,
        DL_ADC12_BURN_OUT_SOURCE_DISABLED, DL_ADC12_TRIGGER_MODE_AUTO_NEXT, DL_ADC12_WINDOWS_COMP_MODE_DISABLED);
    DL_ADC12_setPowerDownMode(ADC12_0_INST,DL_ADC12_POWER_DOWN_MODE_MANUAL);
    DL_ADC12_setSampleTime0(ADC12_0_INST,20);
    DL_ADC12_setSampleTime1(ADC12_0_INST,50);
    DL_ADC12_setSubscriberChanID(ADC12_0_INST,ADC12_0_INST_SUB_CH);
    /* Enable ADC12 interrupt */
    DL_ADC12_clearInterruptStatus(ADC12_0_INST,(DL_ADC12_INTERRUPT_MEM2_RESULT_LOADED
		 | DL_ADC12_INTERRUPT_MEM3_RESULT_LOADED));
    DL_ADC12_enableInterrupt(ADC12_0_INST,(DL_ADC12_INTERRUPT_MEM2_RESULT_LOADED
		 | DL_ADC12_INTERRUPT_MEM3_RESULT_LOADED));
    DL_ADC12_enableConversions(ADC12_0_INST);
}

Here is the Timer0 init function in ti_msp_dl_config.c:

SYSCONFIG_WEAK void SYSCFG_DL_TIMER_0_init(void) {

    DL_TimerG_setClockConfig(TIMER_0_INST,
        (DL_TimerG_ClockConfig *) &gTIMER_0ClockConfig);

    DL_TimerG_initTimerMode(TIMER_0_INST,
        (DL_TimerG_TimerConfig *) &gTIMER_0TimerConfig);
    DL_TimerG_enableClock(TIMER_0_INST);


    DL_TimerG_enableEvent(TIMER_0_INST, DL_TIMERG_EVENT_ROUTE_1, (DL_TIMERG_EVENT_ZERO_EVENT));

    DL_TimerG_setPublisherChanID(TIMER_0_INST, DL_TIMERG_PUBLISHER_INDEX_0, TIMER_0_INST_PUB_0_CH);
}

I guess it must be somewhere I missed. Can you help with this?

Thanks!

Crane

  • Hi Crane,

    You can change the interval time in the TIMER peripheral page as shown below.

    Best Regards,
    Peter

  • Hi Peter,

    Changing this value changes the Timer0's period, but doesn't affect the time interval that triggers the ADC conversion.

    I found although the ADC12 is configured to subscribe the event published by Timer0, but the ADC conversion trigger is not Timer0, but the below setting in the ADC module itself:

    Thanks!

    Crane

  • Hi Crane,

    For the last ADC memory channel, please set the Trigger mode to: "Valid trigger will step..." instead of automatically trigger in Sysconfig. Otherwise, since you have enabled repeat mode, after the last channel finishes acquisition, it will automatically start a new round of ADC acquisition from the beginning and ignore the TIMER Trigger.

    Best Regards,
    Peter Jiang

  • Hi Peter,

    So you mean the Timer 0 should be the trigger if everything else is configured correctly, right? And the proper way to use Timer0 as the ADC trigger should be in this way, not they way that is working now, right?

    I am using Channel 2 and Channel 3 now. When either one is configured as "Valid trigger will stop to next memory conversion register", no ADC conversion interrupt occurs and wrong readings are gotten from ADC.

    Regards,

    Crane

  • Hi Crane,

    adc12_triggered_by_timer_event_LP_MSPM0G3507_nortos_ticlang.zip

    Here is the demo for your reference, use 4-channel and enable all channels result-loaded interrupts, also set timer as 1s to trigger ADC acquisition and set all ADC channels as  "Valid trigger will step...", you can see PA8 will toggle every 1s as below which means the timer every 1s to trigger each channel to sampling.

    So for another example, if you just set the last channel(Channel 3) as "Valid trigger will step to next memory conversion register" and rest of channels as "Trigger will automatically step to next memory conversion register", you will see that every 1s will trigger the whole 4 channels to complete their samplings. because first three channels will automatically generate trigger signal to the next and until the last channel it will wait for timer event to trigger the new round sequence sampling.

    That is to say, "Valid trigger will step to next memory conversion register" means when finish current ADC channel acquisition, it will wait for the next trigger signal whether Software or Timer Event to start next acquisition. And "Trigger will automatically step to next memory conversion register" means it will automatically generate the trigger signal to start the next new ADC acquisition after finish current channel  ADC acquisition, if it is sequence conversion mode, "the next new ADC acquisition" refer to the next memory channel, and if it is single conversion mode, "the next new ADC acquisition" refer to itself.

    Best Regards,
    Peter

  • Hi Peter,

    It is the clear. Thank you for your help!

    Regards,

    Crane