UNIFLASH: Uniflash does not work with TMDSCNCD263P PROC159B (Rev B)

Huey Duong

Part Number: UNIFLASH
Other Parts Discussed in Thread: TMDSCNCD263P,

Tool/software:

Just got 5 new TMDSCNCD263P PROC159B eval boards.

Using Uniflash 9.2.0.5300, unit in DEVBOOT bootmode.

No feature works with RevB board, but works fine with Rev E2 and A boards. Can't program any image to flash. And can't erase flash using utilities.

Does this version of uniflash support Rev B? The flash reset depends on translating the version string from EEPROM = "B".

Current SDK 10.2.0.15 SBL images don't seem to support Rev B boards yet.

====LOG=====================================

[8/25/2025, 11:34:11 PM] [INFO] Cortex_R5_0: GEL Output: Gel files loading Complete

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. Please Wait...

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Crystal Clock present

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: SOP MODE = 0x0000000B

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Dev Boot Mode

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000101

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000100

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Lockstep mode

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Lockstep mode

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 DualCore Reset ***

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS1 DualCore Reset ***

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: R5F ROM Eclipse

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_0 Released

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_1 Released

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_0 Released

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_1 Released

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: L2 Mem Init Complete

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: MailBox Mem Init Complete

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: CORE PLL Configuration Complete

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: PER PLL Configuration Complete

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: SYS_CLK DIVBY2

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Configure all Peripheral clocks()

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks ***

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: RTI0 Clock Enabled (200MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: RTI1 Clock Enabled (200MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: RTI2 Clock Enabled (200MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: RTI3 Clock Enabled (200MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: WDT0 Clock Enabled (200MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: WDT1 Clock Enabled (200MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: WDT2 Clock Enabled (200MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: WDT3 Clock Enabled (200MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: LIN0_UART0 Clock Enabled (160MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: LIN1_UART1 Clock Enabled (160MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: LIN2_UART2 Clock Enabled (160MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: LIN3_UART3 Clock Enabled (160MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: LIN4_UART4 Clock Enabled (160MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: LIN5_UART5 Clock Enabled (160MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Enabling OSPI Clocks

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: OSPI0 Clock Enabled (133MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Enabling I2C Clocks

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: I2C Clock Enabled (48MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Enabling TRACE Clocks

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Trace Clock Enabled (250MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: MCAN0 Clock Enabled (80MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: MCAN1 Clock Enabled (80MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: MCAN2 Clock Enabled (80MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: MCAN3 Clock Enabled (80MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MMCSD Clocks

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: MMCSD Clock Enabled (48MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI0 Clock Enabled (48MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI1 Clock Enabled (48MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI2 Clock Enabled (48MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI3 Clock Enabled (48MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI4 Clock Enabled (48MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: CONTROLSS Clock Enabled (400MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Enabling CPTS Clocks

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: CPTS Clock Enabled (250MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: RGMII5 Clock Enabled (5MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: RGMII50 Clock Enabled (50MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: RGMII250 Clock Enabled (250MHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: TEMPSENSE Clock Enabled (32KHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: XTAL_MMC Clock Enabled (32KHz)

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: GEL Output: ***All IP Clocks are Enabled***

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: AM263Px

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: Board Selected : CC

[8/25/2025, 11:34:12 PM] [INFO] Cortex_R5_0: Part Selected : Standard

[8/25/2025, 11:34:13 PM] [INFO] Cortex_R5_0: GEL Output: CPU reset (soft reset) has been issued through GEL on program load.

[8/25/2025, 11:34:14 PM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x0

[8/25/2025, 11:34:34 PM] [ERROR] Cortex_R5_0: Run failed...

[8/25/2025, 11:34:34 PM] [ERROR] Cortex_R5_0: File Loader: Failed to terminate flash programming: Timed out waiting for target to halt while executing am263px_cc_flasher.out

1 month ago

0 Nilabh Anand 1 month ago

TI__Mastermind 46844 points

Hi Huey,

Apologies you had to face this issue, I am working with the team to create a binary for you. Tomorrow is a holiday in India, let me get back here by friday morning.