TMS570 DMA request lines

Haixiao,

yes I am using TMS570LS20216.

My device.h file was from sample code form TI.  Section for DMA request lines at end of this reply, I had assumed this defined all of the DMA request lines but it appears not to be the case.

I had not looked at the data sheet (well not for some months), but having looked at it again I see in Table 4-3 

Module                                                          DMA Request Sources                                            DMA Request

MIBSPI1                                                      MIBSPI1[1](1)                                                              DMAREQ[0]
MIBSPI1                                                      MIBSPI1[0](2)                                                              DMAREQ[1]

...

MIBADC2 / MIBSPI3 / MIBSPIP5             MIBADC2 event / MIBSPI3[1](1)/ MIBSPIP5[6]       DMAREQ[14]
MIBSPI3 / MIBSPIP5                                 MIBSPI3[0](?) / MIBSPIP5[7]                                        DMAREQ[15]

...

MIBSPI1 / MIBSPI3 / MIBSPIP5               MIBSPI1[14] / MIBSPI3[14] / MIBSPIP5[1](1)          DMAREQ[30]
MIBSPI1 / MIBSPI3 / MIBSPIP5               MIBSPI1[15] / MIBSPI3[15] / MIBSPIP5[0](2)           DMAREQ[31]

Where:

(1) = SPI1, SPI3, SPI5 receive in standard SPI/compatibility mode

(2) = SPI1, SPI3, SPI5 transmit in standard SPI/compatibility mode

(?) appears as a cruxifix in the data sheet but has no footnote.  I assume this is an error and it should read (2) that is the Tx req line.

So:

    SPI3 RX DMA request line is 14 (as you have already stated in your reply and can be seen in Table 4-3)

    SPI3 TX DMA request line is 15 (assuming the crucifix footnote symbol should be a 2 in Table 4-3)

and (for completeness:

    SPI5 RX DMA request line is 30 (from Table 4-3)

    SPI5 TX DMA request line is 31 (from Table 4-3)

Is this correct?

Regards,

Steve

/**********************************************************************************************************************/
/*                     DMA REQUEST LINES                                  */
/**********************************************************************************************************************/

#define NUM_DMA_CHANNELS        16

#define    MIBSPI1_RX_DMA_REQ         0
#define    MIBSPI1_TX_DMA_REQ         1

#define    MIBSPI1_TG1_DMA_REQ         0

#define    MIBSPI1_TG0_DMA_REQ         1

// DMAREQ[2] ----- Reserved
// DMAREQ[3] ----- Reserved

#define    MIBSPI1_TG2_DMA_REQ         4
#define    MIBSPI3_TG2_DMA_REQ         4
#define    DCAN2_IF3_DMA_REQ         4

#define    MIBSPI1_TG3_DMA_REQ         5
#define    MIBSPI3_TG3_DMA_REQ         5
#define    DCAN2_IF2_DMA_REQ         5

#define    MIBSPIP5_TG2_DMA_REQ     6
#define    DCAN1_IF2_DMA_REQ         6

#define MIBADC1_EV_DMA_REQ         7
#define    MIBSPIP5_TG3_DMA_REQ     7

#define    MIBSPI1_TG4_DMA_REQ          8
#define    MIBSPI3_TG4_DMA_REQ         8
#define    DCAN1_IF1_DMA_REQ         8

#define    MIBSPI1_TG5_DMA_REQ          9
#define    MIBSPI3_TG5_DMA_REQ         9
#define    DCAN2_IF1_DMA_REQ         9

#define    MIBADC1_G1_DMA_REQ        10
#define    MIBSPIP5_TG4_DMA_REQ    10

#define    MIBADC1_G2_DMA_REQ        11
#define    MIBSPIP5_TG5_DMA_REQ    11

#define RTI_DMA_REQ0            12
#define    MIBSPI1_TG6_DMA_REQ        12
#define    MIBSPI3_TG6_DMA_REQ        12

#define RTI_DMA_REQ1            13
#define    MIBSPI1_TG7_DMA_REQ        13
#define    MIBSPI3_TG7_DMA_REQ        13

#define    MIBSPI3_TG1_DMA_REQ        14
#define    MIBSPIP5_TG6_DMA_REQ    14
#define MIBADC2_EV_DMA_REQ        14

#define    MIBSPI3_TG0_DMA_REQ        15
#define    MIBSPIP5_TG7_DMA_REQ    15

#define    MIBSPI1_TG8_DMA_REQ        16
#define    MIBSPI3_TG8_DMA_REQ        16
#define    MIBADC2_G1_DMA_REQ        16
#define    DCAN1_IF3_DMA_REQ        16

#define    MIBSPI1_TG9_DMA_REQ        17
#define    MIBSPI3_TG9_DMA_REQ        17
#define    MIBADC2_G2_DMA_REQ        17
#define    DCAN3_IF1_DMA_REQ        17

#define RTI_DMA_REQ2            18
#define    MIBSPIP5_TG8_DMA_REQ    18

#define RTI_DMA_REQ3            19
#define    MIBSPIP5_TG9_DMA_REQ    19

#define HET_DMA_REQ4            20    
#define LIN1_RX_DMA_REQ         20
#define    DCAN3_IF2_DMA_REQ        20

#define LIN1_TX_DMA_REQ         21
#define HET_DMA_REQ5             21
#define    DCAN3_IF3_DMA_REQ        21

#define    MIBSPI1_TG10_DMA_REQ    22
#define    MIBSPI3_TG10_DMA_REQ    22
#define    MIBSPIP5_TG10_DMA_REQ    22

#define    MIBSPI1_TG11_DMA_REQ    23
#define    MIBSPI3_TG11_DMA_REQ    23
#define    MIBSPIP5_TG11_DMA_REQ    23

#define HET_DMA_REQ6             24
#define    MIBSPIP5_TG12_DMA_REQ    24

#define HET_DMA_REQ7             25
#define    MIBSPIP5_TG13_DMA_REQ    25

#define CRC_DMA_REQ0            26
#define    MIBSPI1_TG12_DMA_REQ    26
#define    MIBSPI3_TG12_DMA_REQ    26

#define CRC_DMA_REQ1            27    
#define    MIBSPI1_TG13_DMA_REQ    27
#define    MIBSPI3_TG13_DMA_REQ    27

#define LIN_RX_DMA_REQ             28
#define    MIBSPIP5_TG14_DMA_REQ    28

#define LIN_TX_DMA_REQ             29
#define    MIBSPIP5_TG15_DMA_REQ    29

#define    MIBSPI1_TG14_DMA_REQ    30
#define    MIBSPI3_TG14_DMA_REQ    30
#define    MIBSPIP5_TG1_DMA_REQ    30

#define    MIBSPI1_TG15_DMA_REQ    31
#define    MIBSPI3_TG15_DMA_REQ    31
#define    MIBSPIP5_TG0_DMA_REQ    31

Please make sure:

1) TG group number has nothing do with the DMA request number. It defines the register you are going to use, e.g TG0 means you need to configure DMA0CTRL register.

2) Inside DMAxCTRL register, the RXDMA_MAPx and TXDMA_MAPx defines the DMA request line that transmit and receive are going to use, for example,

RXDMA_MAPx bit 20-23 is 0 /* RXDMA_Mapx*/

means you are going to use SPI DMA channal 0 to receive, if it is SPI3, SPI3 channal 0 in the DATAsheet table is 15.

On the other side, if  

RXDMA_MAPx bit 20-23 is 1 /* RXDMA_Mapx*/

means you are going to use SPI DMA channal 1 to receive, if it is SPI3, SPI3 channal 1 in the DATAsheet table is 14.

Regards,

Haixiao

Haixiao,

thank you for you reply, however is it the case that I need to configure the DMAxCTRL register(s), since I am operating in compatability mode and not multibuffer?

Steve

In compatability mode:

In SPI, you only need to enable the DMA request, e.g.

SPI0_Ptr->SPIINT0_UN.SPIINT0_ST.DMA_REQ_ENA_B1 = 1;

Do not need to configure the DMAxCTRL.

The DMA request are fixed in this case:

#define SPI1_RX_DMA_REQ 0

#define SPI1_TX_DMA_REQ 1

#define SPI3_RX_DMA_REQ 14

#define SPI3_TX_DMA_REQ 15

Which is the table note in the datasheet. the '+' should be '(2)'.

Regards,

Haixiao

Haixiao,

I have now got to the bottom of all this and the problem is solved.

Thank you,

Steve