Tool/software:
After invoking Fapi_issueProgrammingCommandForEccAddresses with invalid ECC values, the write to Flash fails and when the FSM returns to Ready state the bits 4 (INVDAT) and 5 (CSTAT) of the FMSTAT register are set. I can clear bits 4 and 5 by calling Fapi_issueAsyncCommand(Fapi_ClearStatus) and continue. My problem is that unless I cycle power after the invalid data failure, subsequent writes of valid data (using Fapi_issueProgrammingCommand) succeed only a seemingly random number of times at which the commanded data is not written to Flash. The failure does not seem to relate to the specific address that is written. If I cycle power I have consistent success writing valid data to Flash.
Any idea why this would occur? And is there a step I'm missing to restore consistent Flash programming operations?
Thanks,
Cameron