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MCU-PLUS-SDK-AM273X: Multi-core Debug - Grouping Cores

Part Number: MCU-PLUS-SDK-AM273X


Tool/software:

Hello there,

I need to run all three processors (Cortex_R5_0, Cortex_R5_1, C66xx_DSP) together at the same time.

I use the 'Create Core Group' option in Code Composer Studio 20.2.0.

After I group them I try to run all three processors together but the result I get is that the two Cortex_R5 processors run correctly and that the C66xx_DSP processor does not.

In each processor I create one pulse in different IO pins that I catch with an oscilloscope. The pulse from C66xx_DSP processor never occurs.

On the other way when I boot from QSPI the same system project, all three pulses occur correctly.

Does anyone have an idea why that happens? Is there something else I can do to get all these three processors to run at the same time with CCS and JTAG debugger option?

Best Regards,
D.
  • Hi Dimitra,

    I recall in the past, some customers reported that the execution order of the cores may affect the execution result. Can you load and run the program for R5F0, R5F1 and C66x in different order and let us know whether there is a particular order in which the C66x cannot run properly?

    Best regards,

    Ming

  • Hi Ming,

    thank you for your answer. How can I load and run the program for R5F0, R5F1 and C66x in different order?

    Best regards,

    Dimitra

  • Hi Dimitra,

    You will need to ungroup the three cores (R5F0, R5F0 and C66x), then connect to target, load the code and run the code one core at a time (in different orders)

    Best regards,

    Ming

  • Hi Ming,

    I have already done that and it works when I load and run the code first in C66x and then in R5F0 and R5F1.

    The issue is I need the option to run them in a group at the same time. Can I change the order they run when they are grouped? Is there a reason the different running order affects the outcome?

    Best regards,

    Dimitra

  • Hi Dimitra,

    The system is not working, when you run the applications on all three cores at the same time. This issue can be cause by several things:

    1. The memory overlap among applications on cores.

    2. Resource conflict among cores

    3. The IPC communication among cores

    If you cannot find which of above caused the issue and the system runs as expected, then adding certain amount of delay in the beginning of the main() of R5F0 and R5F1 is the simple way to get around this issue.

    Best regards,

    Ming

  • Hi Ming,

    Unfortunately I did not find the reason this issue occurs.

    I recently tried to run the IPC RPMSG ECHO system example (mcu_plus_sdk_am273x_09_02_00_60) as it is, without any interference in the code from me. I faced the same problem. My observation was that it needs to run first the C66x processor and then R5F1 and R5F0 in order to successfully exchange messages. It seems that it always has to be the C66x processor that runs first, in order the system project to run smoothly.

    Can you confirm that? 

    Best regards,

    Dimitra

  • Hi Dimitra,

    Yes. I checked the old JIRA ticket for the IPC issue. The reported issue was the same as the one you reported.

    It is scheduled to be fixed in next release 11.01.00 (end of the Oct. 2025).

    At this point, you will have to add extra delay in in beginning of the main() of R5F0 and R5F1 is to get around this issue.

    Best regards,

    Ming