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MSP432E401Y: Clarification on PWM Output (PF1 – M0PWM1) Not Generating Expected Signal on MSP432E4

Manikandasamy Jayaram
Prodigy 105 points
Part Number: MSP432E401Y

Tool/software:

Dear TI Support Team,

                                  I am working with the MSP432E4 MCU and attempting to generate a PWM signal on PF1 (M0PWM1). The PF1 pin is connected to an FPGA on the other side, where the PWM output will be used as a reference clock.

I have configured the system clock to 120 MHz using the PLL and enabled PWM0. The PF1 pin is configured as GPIO_PF1_M0PWM1, and I am using PWM Generator 0, Output 1. My code is based on TI’s driverlib, and I followed the standard initialization steps:

  1. System clock set to 120 MHz

  2. SysCtlPeripheralEnable() for GPIOF and PWM0

  3. SysCtlPWMClockSet(SYSCTL_PWMDIV_1) for maximum PWM resolution

  4. PF1 configured using GPIOPinConfigure(GPIO_PF1_M0PWM1) and GPIOPinTypePWM()

  5. PWMGenConfigure(PWM0_BASE, PWM_GEN_0, PWM_GEN_MODE_DOWN)

  6. PWMGenPeriodSet() and PWMPulseWidthSet() used to configure period and duty cycle

  7. PWMOutputState() and PWMGenEnable() called

However, I am observing that PF1 remains always high or if i change anything i could not see any output in the PF1 Pin. Even when I configure for a low frequency (e.g., 1 kHz with 50% duty cycle), I do not see the expected waveform.

Could you please clarify the following points?

  1. Is there any additional configuration required for M0PWM1 (PF1) output?

  2. Are there known limitations on maximum PWM frequency achievable on PF1?

  3. Could there be any restriction when driving an FPGA input directly from the PWM pin?

Here below i am giving my code for your reference,

#include <stdint.h>
#include <stdbool.h>
#include "ti/devices/msp432e4/driverlib/driverlib.h"


#define SYSTEM_CLOCK_HZ 120000000 // 120 MHz system clock
#define PWM_FREQUENCY 1000 // 1 kHz for easy observation
#define PWM_DUTY_PERCENT 50 // 50% duty cycle


uint32_t ui32SysClock;
uint32_t ui32Period;

// 1. Configure system clock for 120 MHz using PLL
ui32SysClock = SysCtlClockFreqSet(
(SYSCTL_XTAL_25MHZ |
SYSCTL_OSC_MAIN |
SYSCTL_USE_PLL |
SYSCTL_CFG_VCO_480),
SYSTEM_CLOCK_HZ);

// 2. Enable peripherals
SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);

while(!SysCtlPeripheralReady(SYSCTL_PERIPH_PWM0));
while(!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOF));

// 3. Configure PF1 as M0PWM1
GPIOPinConfigure(GPIO_PF1_M0PWM1);
GPIOPinTypePWM(GPIO_PORTF_BASE, GPIO_PIN_1);

// 4. Disable generator before configuration
PWMGenDisable(PWM0_BASE, PWM_GEN_0);

// Configure generator 0 for down-count mode
PWMGenConfigure(PWM0_BASE, PWM_GEN_0, PWM_GEN_MODE_DOWN);

// 5. Set PWM period and duty cycle
ui32Period = (ui32SysClock / PWM_FREQUENCY);
PWMGenPeriodSet(PWM0_BASE, PWM_GEN_0, ui32Period);

// Set duty cycle = 50%
PWMPulseWidthSet(PWM0_BASE, PWM_OUT_1, (ui32Period * PWM_DUTY_PERCENT) / 100);

// 6. Enable PWM output
PWMOutputState(PWM0_BASE, PWM_OUT_1_BIT, true);

// Enable generator
PWMGenEnable(PWM0_BASE, PWM_GEN_0);

while(1)
{
// Loop forever – PWM runs in hardware
}

I would appreciate your guidance in resolving this issue, as PF1 output is crucial for my design.



Regards,

J.Manikandasamy

  • 0
    TI__Guru**** 190806 points

    Hi,

      The PWM counter is only 16bits. When you use the system clock 120Mhz as the clock source for the PWM, it will overflow the counter for a PWM period of 1kHz. You can use the PWMlockSet to prescale the PWM clock. See below example to prescale the PWM clock to System Clock divide by 16.

    MAP_PWMClockSet(PWM0_BASE, PWM_SYSCLK_DIV_16);

  • 0 in reply to Charles Tsai
    Prodigy 105 points

    Dear charles Tsai,

                               Thanks for your explanation regarding the 16-bit PWM counter limitation and the suggestion to use the MAP_PWMClockSet(PWM0_BASE, PWM_SYSCLK_DIV_16); API.

    I have one follow-up question:

    Even if I configure the PWM clock divider appropriately, is it still possible to generate a 40 MHz output on a PWM pin (e.g., PF1 → M0PWM1)?

    From my calculation:

    • System clock = 120 MHz

    • Desired PWM frequency = 40 MHz

    • Period = 120 MHz / 40 MHz = 3 counts

    This would mean the counter only runs for 3 ticks, giving extremely poor duty-cycle resolution (only 0%, 33%, 66%, or 100%).

    Could you please confirm whether the PWM module can realistically support this frequency, or if I should instead use alternatives such external oscillator to feed my FPGA?


    If possible, kindly share any link or code you may have; that would be greatly appreciated.

    Regards,

    J.Manikandasamy

  • 0 in reply to Manikandasamy Jayaram
    TI__Guru**** 190806 points
    Manikandasamy Jayaram said:

    Even if I configure the PWM clock divider appropriately, is it still possible to generate a 40 MHz output on a PWM pin (e.g., PF1 → M0PWM1)?

    From my calculation:

    • System clock = 120 MHz

    • Desired PWM frequency = 40 MHz

    • Period = 120 MHz / 40 MHz = 3 counts

    This would mean the counter only runs for 3 ticks, giving extremely poor duty-cycle resolution (only 0%, 33%, 66%, or 100%).

    I don't think it is possible. What type of application are you working with? A typical PWM application will have the frequency in the kHz range. I don't your application and can't comment why it would need frequency in the Mhz range. 40Mhz is not possible despite the d/s does not specify the maximum PWM frequency. 

  • 0 in reply to Charles Tsai
    Prodigy 105 points
    Dear Charles Tsai,
             Thank you for your response.

    To provide some context regarding our application — our custom board includes an MSP432E4 microcontroller, an Artix-7 FPGA, and an RFIC. We are currently working on implementing QPSK modulation, which requires a 40 MHz clock input to the FPGA.

    As part of our exploration, we were evaluating whether it's possible to generate this 40 MHz clock using the PWM capabilities of the MSP432E4. I understand from your response that such a frequency may not be feasible via PWM, even though the datasheet doesn’t explicitly mention the maximum PWM frequency.

    We also attempted to use an external 40 MHz crystal oscillator to meet the FPGA's clock requirements, but unfortunately, it didn’t perform as expected in our current setup. This is why I initially raised the ticket — to confirm whether any alternate method of generating a 40 MHz signal from the microcontroller is possible or officially supported.

    If you could share any suggestions or alternate approaches for generating a stable 40 MHz clock (either from the MSP432E4 or other feasible methods), it would greatly help us determine the best path forward.

    Looking forward to your valuable input.

  • 0 in reply to Manikandasamy Jayaram
    TI__Guru**** 190806 points

    The MCU can output a clock through the DIVSCLK pin. However, I/O is not designed for high frequency. You will see noises and distorted signal shape at high frequency like 40Mhz. I don't know if that is suitable for your FPGA.