MCU-PLUS-SDK-AM263PX: Shared mailbox meory

Kunukuntla Geetha

Prodigy 140 points

Part Number: MCU-PLUS-SDK-AM263PX

Tool/software:

Hi,

During RBL, R5 core updates SBL image information in chunks to HSM, chunk size is >= 2KB.

So this chunks will be first placed in shared memory.

As this communication will be between R5F and M4 cores, at which address will the data be placed between in these given shared memory?

In what cases, L2 memory will be used as shared memory? Is there any provision to choose between mailbox memories or L2 memory to place the data?

Regards,

Geetha.

24 days ago

0 Shivasharan Nagalikar 18 days ago

TI__Expert 8630 points

Hi Geetha,

I apologize for the delay and appreciate your patience.

Kunukuntla Geetha said:
As this communication will be between R5F and M4 cores, at which address will the data be placed between in these given shared memory?

For this please refer to Initialization chapter, section 5.2.1.6 IPC in the TRM.

Kunukuntla Geetha said:
In what cases, L2 memory will be used as shared memory? Is there any provision to choose between mailbox memories or L2 memory to place the data?

Regards,

On this please allow me a day or two to update, will check internally and update.

Best Regards, Shiv

0 Shivasharan Nagalikar 16 days ago in reply to Shivasharan Nagalikar

TI__Expert 8630 points

Hi Geetha,

In general like the MAIL Box memory the HW provides option to use the L2 as well. But addition SW logic is needed. For ex: using spinlocks/ interrupts etc something similar to the Mailbox.

Mailbox is the most efficient way to asynchronously exchange the messages between any two processors.

Best Regards, Shiv

0 Kunukuntla Geetha 16 days ago in reply to Shivasharan Nagalikar

Prodigy 140 points

Hi,

Okay!!! I get your point.

But I still need a bit clarity on this.

In this image, HSM_MBOX_SRAM is shared memory between HSM and R5 cores?

and MBOX_SRAM is shared memory among R5 cores?

Thanks and Regards,

Geetha.

Kunukuntla Geetha said:

0 Shivasharan Nagalikar 16 days ago in reply to Kunukuntla Geetha

TI__Expert 8630 points

Hi Geetha,

That is correct.

Best Regards, Shiv

0 Kunukuntla Geetha 15 days ago in reply to Shivasharan Nagalikar

Prodigy 140 points

Hi Shiv,

As I previously mentioned,

Kunukuntla Geetha said:
During RBL, R5 core updates SBL image information in chunks to HSM, chunk size is >= 2KB.

But HSM_MBOX_SRAM size is 2KB. How can R5 send chucks which are greater than 2KB?

Thanks and Regards,

Geetha

+1 Shivasharan Nagalikar 6 days ago in reply to Kunukuntla Geetha

TI__Expert 8630 points

Hi Geetha,

From access perspective, there is no restriction (Ex: use L2 memory when the need is to share more data). Specifically on HSM MBOX query If 2KB is sufficient use the HSM M BOX memory ,if not other L2 memory could also be used. That's exactly the note in the snippet you shared highlights. Hope that clarifies.

Best Regards, Shiv

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MCU-PLUS-SDK-AM263PX: Shared mailbox meory