Other Parts Discussed in Thread: SYSCONFIG
Tool/software:
Hello everyone,
Over the past few days, I’ve been debugging a tricky and sporadic issue that I’d like to share—hopefully it saves someone else some time if they encounter the same problem.
My setup:
- EPWM0–2 used for motor PWM
- SDFM and EnDat running on ICSSG0
- Periodic sampling triggered by IEP0 compare events
- IEP0 is intended to be synchronized with EPWM0, so I disabled the periodic reset of IEP0 via CMP1
The problem: After boot-up, the SDFM and EnDat sampling either worked perfectly or didn’t work at all. I discovered that in the non-working case, IEP0 was never reset by the EPWM sync-out event—even though all configuration registers for EPWM and IEP were identical to the working case.
Interestingly, I could get it working again by manually triggering a software sync-in on EPWM0.
The root cause: EPWM was running at 250 MHz, while IEP0 was set to the sysconfig default of 200 MHz. I suspect the EPWM sync-out signal isn’t properly latched or synchronized by IEP0, causing it to miss every 5th sync event due to the frequency mismatch.
So, depending on whether the sync-out event happens to fall into this “blind spot” during boot-up, the synchronization may fail.
The solution: Increase the IEP0 frequency to ≥ EPWM frequency. This ensures that IEP0 can reliably detect the sync-out events.
Ideally, this condition should be enforced by sysconfig or validated by the SDFM drivers.
Best regards,
Stefan
