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TMS570LC4357-SEP: Output state when VCCIO and VCC under-volt

Aidan Phillips
Prodigy 30 points
Part Number: TMS570LC4357-SEP


Tool/software:

Hello,

I am looking to understand what happens digital outputs in a few different scenarios for the TMS570LC4357-SEP.

Scenario 1:

  • VCCIO falls under 3V (This is the minimum VCCIO voltage from table 6.4)
  • VCC remains in a valid operating range

I understand that section 7.2.2 of the datasheet specifies that when the voltage monitor detects low voltage on the VCCIO rail, the power-on reset signal will be asserted. The datasheet also says that when the power-on reset signal is asserted, the default pulls are asserted.  However, when VCCIO falls out of it's operating range, I suspect that the default pulls are no longer functional.  So it safe to assume it transitions to high-Z cleanly (without glitches)?

Scenario 2:

  • VCCIO falls under 3V
  • VCC falls under 1.14V (This is the minimum VCC voltage from table 6.4)

My understanding is that again from section 7.2.2 when VCC under-volts all outputs go high impedance.  However, i am not sure if this assumes VCCIO is in it's valid operating range or not.  Could you clarify?

  • 0
    Prodigy 30 points

    Following up here, is there any information that can be provided?

  • 0 in reply to Aidan Phillips
    TI__Guru 74186 points

    Hi Aidan,

    VCCIO falls under 3V while VCC remains valid:

    1. When VCCIO falls below the minimum operating voltage (3V), the voltage monitor will detect this condition and assert the power-on reset signal.

    2. While the datasheet indicates that default pulls are asserted during power-on reset, you are correct that these pulls would likely not be functional once VCCIO falls out of its operating range since they depend on VCCIO for proper operation.

      However, I cannot find explicit documentation confirming glitch-free transition to high-impedance state. The device has internal voltage monitoring circuits that should help manage this transition, but the exact behavior is not specified in detail in the available documentation.

    Both VCCIO and VCC fall below minimum:

    1. When VCC falls below 1.14V, all outputs will indeed go to high-impedance state as specified in section 7.2.2(2).

    2. This behavior appears to be independent of VCCIO state, as it's a core-level protection mechanism that takes precedence when VCC fails(2,4).

    3. The internal voltage monitors will detect both VCC and VCCIO undervoltage conditions and assert appropriate reset signals to ensure safe shutdown.

    --
    Thanks & regards,
    Jagadish.

  • 0
    Prodigy 30 points

    Thank you for the response.  There is one scenario we have not covered:

    If VCCIO remains in a valid range but VCC falls under 1.14V:

    • The datasheet says in section 7.2.2 that when the voltage monitor detects this all outputs go high-Z and nPORRST is asserted
    • But the datasheet also says that when nPORRST is asserted, the default pulls are applied to outputs

    I am confused about how these both can be true unless there is a time-delay from the time nPORRST gets asserted and the default pulls are applied.  If this is the case, what is the time delay between high Z and default pulls?  Maybe this is described in table 7-4?

  • 0 in reply to Aidan Phillips
    TI__Guru 74186 points

    Hi Aidan,

    Apologies for the delayed response:

    1. When VCC falls below 1.14V while VCCIO remains valid, there is indeed a specific sequence of events that occurs:

    2. First, the voltage monitor detects VCC falling below 1.14V and triggers the initial response

    3. This causes all outputs to go to high-Z state immediately as a protective measure

    4. The nPORRST signal is then asserted

    5. After nPORRST assertion, the default pulls are applied to the outputs

    --
    Thanks & regards,
    Jagdish.