Tool/software:
Hello,
I am looking to understand what happens digital outputs in a few different scenarios for the TMS570LC4357-SEP.
Scenario 1:
- VCCIO falls under 3V (This is the minimum VCCIO voltage from table 6.4)
- VCC remains in a valid operating range
I understand that section 7.2.2 of the datasheet specifies that when the voltage monitor detects low voltage on the VCCIO rail, the power-on reset signal will be asserted. The datasheet also says that when the power-on reset signal is asserted, the default pulls are asserted. However, when VCCIO falls out of it's operating range, I suspect that the default pulls are no longer functional. So it safe to assume it transitions to high-Z cleanly (without glitches)?
Scenario 2:
- VCCIO falls under 3V
- VCC falls under 1.14V (This is the minimum VCC voltage from table 6.4)
My understanding is that again from section 7.2.2 when VCC under-volts all outputs go high impedance. However, i am not sure if this assumes VCCIO is in it's valid operating range or not. Could you clarify?