Other Parts Discussed in Thread: UNIFLASH, CSD
Tool/software:
Please provide your answers for the following queries.
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ECC
- Will the ECC bits are enabled by RBL development boot mode(debug)?
- What is the behavior when ECC fails when RBL is running?
- During a data abort exception, how can one differentiate between a double-bit error and an inject-only mode trigger?
- Which status flag will get set when 2bit ECC error is injected in TCM memory?
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PBIST
- As per your reply failures like certificate validation or SBL integrity check failures or PBIST failure on the MSS ROM are available in logger. Apart from these failures RBL may be performing other tests as well. Kindly share the complete list of failures that can be detected by the RBL.
- Can our customized SBL be used to test TCMA and TCMB memory without using PBIST module?
- Please explain in detail how to take care of the below scenario under section 13.6.6.3.
R5SS VIM Memories – Since ISR is stored in VIM memories, if VIM memories are to be tested, polling on interrupt line should be done and not ISR execution.
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OSPI (8S) and xSPI (8D), eXecute-In-Place (XIP)
- What is XIP (Execute In Place), and how exactly does it work?
- How does XIP execute instructions step by step? Are any Flash APIs required?
- What is the expected execution speed in XIP mode? For example, if the CPU runs at 400 MHz, will execution performance be compromised?
- Since code typically contains multiple segments, which segments remain in Flash during XIP, and which segments are copied to RAM before execution (will data segment be moved to RAM while executing the code)?
- What exactly is demonstrated in the XIP example code provided in the SDK?
- What are FSS region_0 (0x6000_0000) and FSS region_1 (0x8000_0000), and why are they designated as boot space (TRM page 1506)? What does "address remappable" mean in this context?
- Is the MCELF XIP final image encrypted? What is x509 certificate? If yes, how is encryption handled, and what is the role of x509 certificates?
- Is the OTFA (On-The-Fly Authentication) authenticator required in the XIP flow?
- Is it necessary to implement code to read the SFDP (Serial Flash Discoverable Parameters) header structure, or is it handled automatically by hardware/software?
- Once XIP is configured, will code execution happen automatically, or do we need to implement additional logic to execute instruction by instruction?
- Can the Boot DIP switches be hardwired to xSPI mode? If so, can Uniflash still update/flash the image in xSPI mode without changing DIP switches?
- How can we flash multiple images on the same core using Uniflash?
- We are working on custom SBL_xSPI. While developing a custom SBL_xSPI, what key considerations should we keep in mind?
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CPSW
- How the CPDMA, Host port and MAC ports are connected ?
- To Host and From Host terms are confusing, Does To Host mean Transmit ?
- TI documentation has a lot of typo errors and important driver registers are missing. E.g., MAC Port control registers for Port 1 and Port 2 are missing in AM263x Register Addendum (Rev E). I have raised a query in TI forum and the TI representative agreed that these registers are missing, but I have not received any documentation/information on these registers yet. It has been 14 days since the query is raised, how am I suppose to implement the driver with missing registers in processor document ?
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MMCSD
- When the host sends CMD 2 to get CID register, the response it receives is 136 bits in the RSP10, RSP32, RSP54, RSP76 response registers. Since they can hold 128 bits of response bits corresponding to the 128 bits of CID register, do we need to shift 1 byte of data left to get the CID register value as per mmcsd_parse.c(Function : MMCSD_parseCIDEmmc)?.
Same with CMD 9 to get CSD register too. When the response is not shifted left, the value received for TRAN_SPEED on CSD Bits is [103:96] is 0x32, which is 25Mhz. If the response bytes are shifted left, the values of CSD registers are not relevant. - We can see the functions for MMC are implemented in the below path of TI Git 'github.com/.../mmcsd_v0.c'.
Which version of SDK can we install for the latest files for MMC? Also need a working example project for MMC.
- When the host sends CMD 2 to get CID register, the response it receives is 136 bits in the RSP10, RSP32, RSP54, RSP76 response registers. Since they can hold 128 bits of response bits corresponding to the 128 bits of CID register, do we need to shift 1 byte of data left to get the CID register value as per mmcsd_parse.c(Function : MMCSD_parseCIDEmmc)?.
