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AM263P4-Q1: How to reset ESM Raw status register on ECC injection

Minni Yadav
Prodigy 10 points
Part Number: AM263P4-Q1
Other Parts Discussed in Thread: AM2632

Tool/software:

When 1 bit error is injected in ATCM R5SS0 memory and read memory to trigger ECC error. This will set following registers
MSS_CTRL
Set 50D18084h and 50D18088h for 1 bit error
Set 50D18094h and 50D18098h for 2 bit error
ESM
Set 52D00420h and 52D00424h for ECC Core 0.


According to SDK sdl_ecc_r5_atcm0 example, to clear TCM errors, writing 1 to 0x50D18084h and 0x50D18088h for 1 bit error and writing 1 to 0x52D0042C (ESM_PCR_GENERATED_MEMORY_MAP_ERR_GRP_INTR_EN_CLR_J Register).
This will reset 0x52D00424h but 0x52D00420h is still set to 1.

How to reset the 0x52D00420h ESM_PCR_GENERATED_MEMORY_MAP_ERR_GRP_RAW_J Register to clear TCM errors?

  • 0
    Prodigy 10 points

    I've also tried correcting error by restoring the correct data in ATCM memory and clear the MSS_CTRL and ESM STS flags. Still ESM RAW register is set to 1.

  • 0 in reply to Minni Yadav
    TI__Guru 70911 points

    Hi Minni Yadav,

    My apologies for the delayed response,

    I am working on your issue now and will give my updates as soon as possible.

    --

    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    TI__Guru 70911 points

    Hi Minni Yadav,

    Minni Yadav said:
    According to SDK sdl_ecc_r5_atcm0 example, to clear TCM errors, writing 1 to 0x50D18084h and 0x50D18088h for 1 bit error and writing 1 to 0x52D0042C (ESM_PCR_GENERATED_MEMORY_MAP_ERR_GRP_INTR_EN_CLR_J Register).
    This will reset 0x52D00424h but 0x52D00420h is still set to 1.

    Before writing 1 to the 0x52D0042C, also write one to the 0x52D00424.

    Try below sequence:

    1. First write one to the 0x52D00424, this should clear the interrupt status as per the TRM:

    2. And after this now you can write 1 to the 0x52D0042C, this should clear error status register and also disables the mask of events.

    Could you please try this sequence and let me know the results.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 10 points

    I attempted the sequence described above. Using only the first step, I am able to reset the RAW register.

    I perform one-bit and two-bit ECC error injections. After a one-bit error is injected, the ESM status flags are set. After clearing the ESM interrupt status (by writing 1 to 0x52D00424), I inject a two-bit error and read the corrupted memory.

    However, the ESM status registers are not set. When executed individually, both one-bit and two-bit injections set the status flags as expected. Yet, if a one-bit error is injected and its status flags are subsequently cleared, a subsequent two-bit injection fails to set the corresponding flags.

    What additional steps are required to perform error injections sequentially (i.e., one immediately after the other)?

  • 0 in reply to Minni Yadav
    TI__Guru 70911 points

    Hi Minni Yadav,

    Apologies for the delayed response:

    jagadish gundavarapu said:
    2. And after this now you can write 1 to the 0x52D0042C, this should clear error status register and also disables the mask of events.

    As i mentioned here i think this second one also clears the enable mask, that means it will stop further interrupt triggers for corresponding group. 

    Try below sequence:

    After one-bit error

    1. Write one to the 0x52D00424, this should clear the interrupt status.

    Now perform two-bit error injections:

    2. Again, write one to the 0x52D00424, this should clear the interrupt status.

    Now both injections tests completed right, so now you can write 1 to the 0x52D0042C, this should clear error status register and also disables the mask of events.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 10 points

    Hi,

    After finishing the 1-bit error injection, when I try the 2-bit error injection, it doesn’t work and the status flags don’t get set. 

    Could you please guide me in understanding why the 2-bit error injection is not occurring?

  • 0 in reply to Minni Yadav
    TI__Guru 70911 points

    Hi Minni Yadav,

    Apologies for the delayed response! 

    Are you still stuck with this issue, if yes then i will try to reproduce your issue at my end and will try to provide further updates on this issue.

    --

    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 10 points

    Yes, issue still exists. I am observing inconsistent ESM flag behavior during ECC error injection testing on the AM2632 controller. Below are the detailed test scenarios and observations:

    Scenario 1: ATCM Core 0 Memory

    • Inject a 1-bit error and clear it.
    • Then inject a 2-bit error and observe the ESM status registers.

    Observation:
    When the 1-bit error is injected first followed by the 2-bit error, the ESM status flags are not set for the 2-bit error.
    However, in the SDK reference example, the order is reversed (2-bit error injected first, then 1-bit error), and in that sequence, the ESM flags are set correctly.

    Query:
    Why does the ESM fail to set status flags when the 1-bit error is injected before the 2-bit error?

    Scenario 2: ICSSM Memory

    • Inject a 1-bit error for RAM ID 1 and clear it.
    • Then inject a 1-bit error again for RAM ID 2 and check the ESM register flags.

    Observation:
    When injecting 1-bit errors sequentially for different RAM IDs within the same ICSSM memory, the ESM flags are set only for the first RAM ID, while the subsequent RAM IDs do not trigger ESM flag updates.

    Query:
    Why are the ESM flags not set for subsequent RAM IDs when injecting 1-bit errors sequentially within the same memory instance?