Part Number: LP-AM261
Tool/software:
Hi Team,
I am working on AM261x-LP, with IAR toolchain using CMake Build system. Since AM261x was not supported by IAR(9.5), I upgraded my IAR to 9.7 which has the support now.
Initially I had used TIClang 4.0.1 with CMakebuild system. I was able to build & flash Secondary Bootloader and a sample blinky application by enabling the XIP mode.
With TIClang I didnt have any issues, but I want to use IAR toolchain. For that I started with Secondary Bootloader(SBL_OSPI), I am able to build the SBL but the generated binary size is too large. Below is the size differences of both toolchains:
a) TI Compiler: out image size -> 983KB and Post build bin size is 218KB, and able to sign using mcu_rom_image_gen.py to generate sbl_ospi.tiimage.
b) IAR Compiler: out image size -> 1.6MB and Post build bin size is 1.75Gb.
Since it is bootloader mcu_rom_image_gen.py expects bin file size to be less than 985KB.
Changes done for IAR CMake build:
1) Changed Baremetal kernel files to be compatible with IAR , Since existing Assembly files support TIClang only.
Files from mcu_plus_sdk_am261x_10_02_00_15 :
boot_armv7r_asm.S
CacheP_armv7r_asm.S
Cpuid_armv7r_asm.S
HwiP_armv7r_asm.S
HwiP_armv7r_handlers_nortos_asm.S
HwiP_armv7r_vectors_nortos_asm.S
MpuP_armv7r_asm.S
PmuP_armv7r_asm.S
Sample Snip of CacheP_armv7r_asm Assembly:
Before:
/* FUNCTION DEF: void CacheP_enableL1d(void) */
.global CacheP_enableL1d
.type CacheP_enableL1d,%function
.section ".text.cache","ax",%progbits
.arm
.align 2
CacheP_enableL1d:
mrc p15, #0, r0, c1, c0, #0 // read SCR register
orr r0, r0, #0x0004 // set C bit (bit 2) to 1
dsb
mcr p15, #0, r1, c15, c5, #0 // Invalidate entire data cache
mcr p15, #0, r0, c1, c0, #0 // L1D cache enabled
bx lr
After:
/* FUNCTION DEF: void CacheP_enableL1d(void) */
PUBLIC CacheP_enableL1d
SECTION .text_cache:CODE:NOROOT(2) ; keep function in .text, align 2 bytes
ARM
CacheP_enableL1d:
mrc p15, #0, r0, c1, c0, #0 // read SCR register
orr r0, r0, #0x0004 // set C bit (bit 2) to 1
dsb
mcr p15, #0, r1, c15, c5, #0 // Invalidate entire data cache
mcr p15, #0, r0, c1, c0, #0 // L1D cache enabled
bx lr
2) IAR compiler Flags in CMake:
# Compilers
set(CMAKE_C_COMPILER "${TOOLCHAIN_BIN}/iccarm.exe")
set(CMAKE_CXX_COMPILER "${TOOLCHAIN_BIN}/iccarm.exe")
set(CMAKE_ASM_COMPILER "${TOOLCHAIN_BIN}/iasmarm.exe")
set(CMAKE_AR "${TOOLCHAIN_BIN}/iarchive.exe")
set(CMAKE_LINKER "${TOOLCHAIN_BIN}/ilinkarm.exe")
set(CMAKE_OBJCOPY "${TOOLCHAIN_BIN}/ielftool.exe")
a)C- CPP Flags: set(TARGET_MCU_FLAGS
"--cpu=cortex-r5"
"--fpu=vfpv3"
"--endian=little"
"--thumb"
)
b)Common-Flags: set(COMPILER_FLAGS
"-e"
"--diag_suppress=Pa050"
"--no_path_in_file_macros"
"--no_cse"
"--no_unroll"
"--no_inline"
"--no_code_motion"
"--no_tbaa"
"--no_clustering"
"--no_scheduling"
"--mfc"
)
c)CMAKE_ASM_FLAGS: set(CMAKE_ASM_FLAGS
${TARGET_MCU_FLAGS}
"-s+"
"-w+"
# "-r"
"-M<>"
)
d)Debug & Release Flags:
set(CMAKE_C_FLAGS_DEBUG "-On --debug")
set(CMAKE_C_FLAGS_RELEASE "-Os -guard_calls")
e) Linker Flags:
set(CMAKE_EXE_LINKER_FLAGS
"--map +"
"--inline"
"--no_exceptions"
"--vfe"
"--merge_duplicate_sections"
"--redirect _Printf=_PrintfLargeNoMb"
"--redirect _Scanf=_ScanfFullNoMb"
"--no_remove"
)
3)Changes to linker script(.icf) to align with sections defined:
/* Stack and heap sizes */
define symbol __ICFEDIT_size_cstack__ = 0x2000; /* 8kb */
define symbol __ICFEDIT_size_heap__ = 0x8000; /* 32768 */
/* R5 mode-specific stacks */
define symbol __IRQ_STACK_SIZE = 0x1000; /* 4096 */
define symbol __FIQ_STACK_SIZE = 0x0100; /* 256 */
define symbol __SVC_STACK_SIZE = 0x1000; /* 4096 */
define symbol __ABORT_STACK_SIZE = 0x0100; /* 256 */
define symbol __UNDEFINED_STACK_SIZE = 0x0100; /* 256 */
/*------------------------------------------------------------------*/
/* MEMORY regions */
/*------------------------------------------------------------------*/
define memory mem with size = 4G;
define region R5F_VECS = mem:[from 0x00000000 to 0x000000FF];
define region R5F_TCMA = mem:[from 0x00000100 to 0x00007FFF];
define region R5F_TCMB0 = mem:[from 0x00080000 to 0x00087FFF];
define region MSRAM_VECS = mem:[from 0x70002000 to 0x700020FF];
define region MSRAM_0 = mem:[from 0x70002100 to 0x70031FFF];
define region MSRAM_HSMRT = mem:[from 0x70032000 to 0x70071FFF];
define region MAILBOX_HSM = mem:[from 0x44000000 to 0x440003CD];
define region MAILBOX_R5F = mem:[from 0x44000400 to 0x440007CD];
/*------------------------------------------------------------------*/
/* BLOCKS for stacks + heap */
/*------------------------------------------------------------------*/
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { rw section CSTACK };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block IRQ_STACK with alignment = 8, size = __IRQ_STACK_SIZE { rw section IRQ_STACK };
define block FIQ_STACK with alignment = 8, size = __FIQ_STACK_SIZE { rw section FIQ_STACK };
define block SVC_STACK with alignment = 8, size = __SVC_STACK_SIZE { rw section SVC_STACK };
define block ABT_STACK with alignment = 8, size = __ABORT_STACK_SIZE { rw section ABT_STACK };
define block UND_STACK with alignment = 8, size = __UNDEFINED_STACK_SIZE { rw section UND_STACK};
place in MSRAM_0 {
readwrite section .bss,
readwrite section .sysmem,
readwrite section .stack,
block CSTACK,
block HEAP,
block IRQ_STACK,
block FIQ_STACK,
block SVC_STACK,
block ABT_STACK,
block UND_STACK
};
/*------------------------------------------------------------------*/
/* PLACEMENT */
/*------------------------------------------------------------------*/
place at address mem:0x00000000 { readonly section .intvec };
place in MSRAM_VECS {
readonly section .sbl_init_code,
readonly section .vectors
};
place in MSRAM_0
{
/* text/ro */
readonly section .text,
readonly section .text_hwi,
readonly section .text_pmu,
readonly section .text_cache,
readonly section .text_boot,
readonly section .rodata,
readonly section .rodata_cfg,
readonly section .iar.init_table,
readonly section .data.pmu_init,
/* data/rw */
readwrite section .data,
readwrite section .data.pmu,
};
place in MSRAM_HSMRT {
readonly section .rodata.hsmrt
};
place in MAILBOX_HSM {
readwrite section .bss.sipc_hsm_queue_mem
};
place in MAILBOX_R5F {
readwrite section .bss.sipc_secure_host_queue_mem
};
/* Mark as NOLOAD */
do not initialize { section .bss.sipc_hsm_queue_mem };
do not initialize { section .bss.sipc_secure_host_queue_mem };
There is no change in Application code, I am using same for both toolchains.
But in my application code I am using "__attribute " as below, do I need to to use #pragma instead of __attribute ? or anything else could make it work .
#define RODATA_CFG_SECTION __attribute__((section(".rodata_cfg")))
/* ----------- CacheP ----------- */
const CacheP_Config gCacheConfig RODATA_CFG_SECTION = {
.enable = 1,
.enableForceWrThru = 0,
};
I need to make AM261x compatible with IAR toolchain.
Any help is greatly appreciated. Thanks!
