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TMS570LS3137: Start up : pbistSelfCheck() from HalCoGen VS SAfeTIs SL_SelfTest_PBIST()

Marc Cifuentes
Intellectual 280 points

Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Tool/software:

Hello,

Regarding the usage of SL_SelfTest_PBIST to do a pre test of the PBIST algorithm using ROM, can you confirm me that : 

    /* Run a diagnostic check on the memory self-test controller.
     * This function chooses a RAM test algorithm and runs it on an on-chip ROM.
     * The memory self-test is expected to fail. The function ensures that the PBIST controller
     * is capable of detecting and indicating a memory self-test failure.
     */
    pbistSelfCheck();  
--> generated by HalCogen
can be replaced by : 
SL_SelfTest_PBIST(PBIST_EXECUTE,
                              PBIST_RAMGROUP_02_STC_ROM,
                              PBISTALGO_TRIPLE_READ_SLOW_READ | PBISTALGO_TRIPLE_READ_FAST_READ);
SL_SelfTest_PBIST(PBIST_EXECUTE,
                              PBIST_RAMGROUP_01_PBIST_ROM,
                              PBISTALGO_TRIPLE_READ_SLOW_READ | PBISTALGO_TRIPLE_READ_FAST_READ);
to cover the PBIST check selftest as described in the SPNA106D : Initialization of HerculesTm ARM® CortexTm-R4F Microcontrollers
Thank you ! 
Regards,
Marc
  • +1
    TI__Guru* 78256 points

    Hi Marc,

    Apologies for the delayed response!

    We have one internal AI tool which can analyze all the documents of this controller along with all the e2e data base and i got some useful response from it, please refer this response in the first place, if you need any further help i will do it:

    Yes, the pbistSelfCheck() function generated by HalCoGen can be replaced with the two SL_SelfTest_PBIST() calls you've specified. Here's the detailed explanation:

    1. The original pbistSelfCheck() function is designed to run a diagnostic check on the memory self-test controller by testing an on-chip ROM and expecting a failure to verify the PBIST controller can detect failures.

    2. Your proposed replacement using:

    SL_SelfTest_PBIST(PBIST_EXECUTE,
    PBIST_RAMGROUP_02_STC_ROM,
    PBISTALGO_TRIPLE_READ_SLOW_READ | PBISTALGO_TRIPLE_READ_FAST_READ);
    SL_SelfTest_PBIST(PBIST_EXECUTE,
    PBIST_RAMGROUP_01_PBIST_ROM,
    PBISTALGO_TRIPLE_READ_SLOW_READ | PBISTALGO_TRIPLE_READ_FAST_READ);

    This implementation is valid because:

    1. It tests both the STC ROM (PBIST_RAMGROUP_02_STC_ROM) and PBIST ROM (PBIST_RAMGROUP_01_PBIST_ROM) which are the essential components for verifying PBIST functionality(0).

    2. The PBIST engine uses a dedicated on-chip ROM that holds the test algorithms, so you don't need to load algorithms separately(0).

    3. The implementation follows the initialization sequence described in SPNA106D for Hercules ARM Cortex-R4F microcontrollers.

    Important considerations:

    1. Make sure to disable all enabled interrupts (UART, RTI, PBIST) before performing the PBIST test(1).

    2. The PBIST controller is a programmable test engine specifically designed for testing internal SRAM and ROM on the device(5).

    3. The test algorithms are stored in ROM and don't need to be loaded separately(0).

    Note: While this implementation is valid, ensure proper error handling and status checking of the PBIST execution results. The PBIST test results should be monitored for proper completion and any potential error conditions.

    The lexical interpolation values were varied (0.005, 0.05, 0.01, 0.008) across searches to capture both exact matches and contextually relevant information about PBIST implementation. The final value of 0.008 provided the most relevant results for specific PBIST implementation details.

    --
    Thanks & regards,
    Jagadish.