Tool/software:
Dear expert
Customer following our AM2432 EVM(LP-AM243 Evaluation board | TI.com) that use as SN74LV1T34DCKR clock buffer to design their hardware but find there is issue that the CLK signal of the 3V3, after passing through this buffer, becomes CLK of the 1V8, the rising edge will slow down and the CLK waveform will deform. Is there any possible risks of this design?
3V3 CLK signal: Rising and falling edge symmetrical, similar to square wave
1V8 CLK signal: Rising and falling edges slow, rising and falling edges more noticeably, duty > 50%
Check the buffer's datasheet and find that under the 1V8 power supply, the buffer is recommended to use up to 15MHz, not suitable for the current 25MHz clock design.
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