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UNIFLASH: dslite with mcelf_xip fails to program XIP section with address 0xE000_0000

Huey Duong
Intellectual 400 points
Part Number: UNIFLASH
Other Parts Discussed in Thread: TMDSCNCD263P

Tool/software:

Using Uniflash 9.3.0.5401.  TMDSCNCD263P Rev A.

Generated standalone command line package using onboard XDS110 to program SBL, mcelf and mcelf_xip images.

Works fine from the Uniflash GUI. 

But when running dslite-Cortex_R5_0.bat from CLI it consistently fails trying to program mcelf_xip image using address 0xE000_0000.

PS C:\Work\uniflash_windows> .\dslite-Cortex_R5_0.bat
Executing default command:
> dslite --mode flash -c user_files/configs/AM263Px.ccxml -l user_files/settings/generated.ufsettings -s VerifyAfterProgramLoad="No verification" -e -f -v "user_files/images/sbl_ospi_multicore_elf.release.tiimage,0x60000000" "user_files/images/proj_sys_tmdscncd263p.mcelf,0x60081000" "user_files/images/proj_sys_tmdscncd263p.mcelf_xip,0xE0000000"

...

error: Cortex_R5_0: File Loader: Verification failed: Values at address 0xE0000000 do not match (expected: 0x7F, actual: 0xD0) Please verify target memory and memory map.
Finished: 41%
Failed: File: Multiple Files: a data verification error occurred, file load failed.

Here's the full log. 

uniflash_dslite_xip_log.txt

The same issue is seen when using appimage and address 0xF000_0000.

Is there a special step or command to program the XIP image?  and why did the standalone command line package not generate the proper commands?

Thanks for the help.

  • 0
    TI__Guru**** 473471 points

    Hello,

    Can you also copy&paste all the text in the UniFlash GUI Console for the working case to a text file and attach the file to this thread?

    Thanks

    ki

  • 0 in reply to Ki
    Intellectual 400 points

    Here is a working case with verbose turned on.

    [9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. Please Wait...
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Crystal Clock present
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: SOP MODE = 0x00000003
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: OSPI (8S) - Octal Read Mode
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 DualCore Reset ***
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS1 DualCore Reset ***
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: R5F ROM Eclipse
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_0 Released
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_1 Released
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_0 Released
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_1 Released
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: L2 Mem Init Complete
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: MailBox Mem Init Complete
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Configure all Peripheral clocks()
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks ***
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: RTI0 Clock Enabled (200MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: RTI1 Clock Enabled (200MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: RTI2 Clock Enabled (200MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: RTI3 Clock Enabled (200MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: WDT0 Clock Enabled (200MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: WDT1 Clock Enabled (200MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: WDT2 Clock Enabled (200MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: WDT3 Clock Enabled (200MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: LIN0_UART0 Clock Enabled (160MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: LIN1_UART1 Clock Enabled (160MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: LIN2_UART2 Clock Enabled (160MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: LIN3_UART3 Clock Enabled (160MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: LIN4_UART4 Clock Enabled (160MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: LIN5_UART5 Clock Enabled (160MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Enabling OSPI Clocks
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: OSPI0 Clock Enabled (133MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Enabling I2C Clocks
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: I2C Clock Enabled (48MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Enabling TRACE Clocks
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Trace Clock Enabled (250MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: MCAN0 Clock Enabled (80MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: MCAN1 Clock Enabled (80MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: MCAN2 Clock Enabled (80MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: MCAN3 Clock Enabled (80MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MMCSD Clocks
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: MMCSD Clock Enabled (48MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI0 Clock Enabled (48MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI1 Clock Enabled (48MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI2 Clock Enabled (48MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI3 Clock Enabled (48MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI4 Clock Enabled (48MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: CONTROLSS Clock Enabled (400MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Enabling CPTS Clocks
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: CPTS Clock Enabled (250MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: RGMII5 Clock Enabled (5MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: RGMII50 Clock Enabled (50MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: RGMII250 Clock Enabled (250MHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: TEMPSENSE Clock Enabled (32KHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: XTAL_MMC Clock Enabled (32KHz)
[9/29/2025, 1:55:37 PM] [INFO] Cortex_R5_0: GEL Output: ***All IP Clocks are Enabled***
[9/29/2025, 1:55:38 PM] [INFO] Cortex_R5_0: GEL Output: CPU reset (soft reset) has been issued through GEL on program load.
[9/29/2025, 1:55:38 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x60000000 of Length 0x00007ff0
[9/29/2025, 1:55:39 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x60007ff0 of Length 0x00007ff0
[9/29/2025, 1:55:39 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x6000ffe0 of Length 0x00007ff0
[9/29/2025, 1:55:39 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x60017fd0 of Length 0x00007ff0
[9/29/2025, 1:55:39 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x6001ffc0 of Length 0x00007ff0
[9/29/2025, 1:55:39 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x60027fb0 of Length 0x00007ff0
[9/29/2025, 1:55:39 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x6002ffa0 of Length 0x00007ff0
[9/29/2025, 1:55:39 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x60037f90 of Length 0x00007ff0
[9/29/2025, 1:55:39 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x6003ff80 of Length 0x00007ff0
[9/29/2025, 1:55:39 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x60047f70 of Length 0x00002e3d
[9/29/2025, 1:55:39 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x60081000 of Length 0x00007ff0
[9/29/2025, 1:55:40 PM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x60088ff0 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x60090fe0 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x60098fd0 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x600a0fc0 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x600a8fb0 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0x600b0fa0 of Length 0x00001fcc
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe0000000 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe0007ff0 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe000ffe0 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe0017fd0 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe001ffc0 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe0027fb0 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe002ffa0 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe0037f90 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe003ff80 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe0047f70 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe004ff60 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe0057f50 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe005ff40 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe0067f30 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe006ff20 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe0077f10 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe007ff00 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe0087ef0 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe008fee0 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe0097ed0 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe009fec0 of Length 0x00007ff0
[9/29/2025, 1:55:47 PM] [INFO] Cortex_R5_0: Writing Flash @ Address 0xe00a7eb0 of Length 0x0000539c
[9/29/2025, 1:55:49 PM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x81000
[9/29/2025, 1:55:56 PM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x300000
[9/29/2025, 1:56:06 PM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x500000
[9/29/2025, 1:56:07 PM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x700000
[9/29/2025, 1:56:10 PM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x900000
[9/29/2025, 1:56:13 PM] [SUCCESS] Program Load completed successfully.

  • 0 in reply to Huey Duong
    TI__Guru**** 473471 points

    Thank you. We are investigating.

  • 0 in reply to Ki
    Intellectual 400 points

    Hi Ki, any update on this issue?  Thanks.

  • 0 in reply to Huey Duong
    TI__Guru**** 473471 points

    Huey,

    Can you provide the images you are using? It will help investigation. You can send it to me via private E2E chat if you do not wish to share public.

    Note that I don't need your exact image. I just need any example that can reproduce the issue.

    Thanks

    ki

  • 0 in reply to Ki
    Intellectual 400 points

    Here's a Standalone Command Line Package generated using Uniflash 9.3 and building optiflash_xip_benchmark_am263px-cc example from CCS.

    (looks like the zip was too big.  110M.  I'll send it privately.

    0741.log.txt