UNIFLASH: Stuck at "GEL Expression: OnTargetConnect()" or "Enabling RTI[0:3] Clocks" when loading

Huey Duong

Intellectual 370 points

Part Number: UNIFLASH
Other Parts Discussed in Thread: TMDSCNCD263P, AM263P4, AM2634

Tool/software:

Using uniflash 9.2.0 and 9.3.0 on TMDSCNCD263P and BOOTMODE=OSPI(8s)

Uniflash tools keep hanging when it reaches:

"Enabling RTI[0:3]Clocks" and "GEL Expression: OnTargetConnect()"

I don't have the exact sequence to replicate this, but switching applications, switching between 9.2 and 9.3, computer going to sleep may have something to do with it.

Once it gets into this state, it will stay in this state unless I close the tool and run fsclean.bat. And even this sometimes needs to be done several times. Including disconnect the USB cable to XDS110 sometimes.

I've tried reinstalling both versions.

How can I make this experience better for the team. Seems people are seeing this quite often and are getting very frustrated with having to restart and reselect the files.

And when we are using on a remote machine, it is not convenient to pull the debug cable.

Any help to improve this is appreciated.

4 days ago

0 Ki 3 days ago

TI__Guru**** 465431 points

Hello,

Typically this is an issue with the device being in a bad state. However, it is odd that clearing the cache resolves this. It could be the cache getting corrupted when switching between versions.

Based on the nature of the error, it looks like it occurs when UniFlash simply connects to the target and before any flashing is attempted.

I will try to reproduce this on my end.

0 Huey Duong 3 days ago in reply to Ki

Intellectual 370 points

Thanks, i think a clue may have to do bootmode left in OSPI(8s) and when programming a new image, the board is booted and actively running an application.

0 Ki 3 days ago in reply to Huey Duong

TI__Guru**** 465431 points

Thanks for the hint. That could explain why a power cycle helps. However clearing the cache wouldn't have an impact on that case.

0 Huey Duong 3 days ago

Intellectual 370 points

Another hint. I've set up 2 AM263P4 EVAL-CC boards on the same host computer, hence 2 XDS110 onboard emulators over USB.

Using uniflash to generate Standalone CLI package, then updated the package to support programming 2 boards (based on XDS' serial numbers) using dslite.

I took both the program and verify at once and the program and verify independently examples.

Using the program and verify at once example, ping ponging between the boards caused it to hang, although retrying worked using dslite. (in the past, when this happened on uniflash, it does not work until we do fsclean a couple of times).

But when I ping pong using the independent program then verify, it "seems" to work.

Maybe something to do with verify?

Here's the full log

.dslite_ontarget_hang.txt

0 Huey Duong 3 days ago in reply to Huey Duong

Intellectual 370 points

Spoke too soon. It also hangs when running verify after programming. But not as often. But the advantage of using this method is when it does hang, I just retry. Also the script seems to complete much faster on the retry attempt.

0 Ki 10 hours ago in reply to Huey Duong

TI__Guru**** 465431 points

Huey Duong said:
Another hint. I've set up 2 AM263P4 EVAL-CC boards on the same host computer, hence 2 XDS110 onboard emulators over USB.

Did you ever see this when only one target was connected?

In any cause I don't think this is the issue. I find the AM2634 a bit unreliable in general as I often have to do various resets or power cycles to the get the R5 cores in a good state after some usage.

When the device is in that bad state in UniFlash, if you simply try to view memory instead of load), do you get the same OnTargetConnect issue?

0 Huey Duong 10 hours ago in reply to Ki

Intellectual 370 points

Yes, it definitely does this only when there is one target connected.

=) Please help make the AM2634 to be more stable with resets and tools. It is quite frustrating for me and the team to constantly have to power cycle boards, pull USB cable, restart apps, clear cache and sometimes reboot in order to get this chip to work. This should not be the case.

The next time it happens on a single unit again, I will post the results of other features.

0 Ki 10 hours ago in reply to Huey Duong

TI__Guru**** 465431 points

I hear that CCS 20.3.0 has some improved device support files for AM263 that help the experience. I'm not sure if UniFlash 9.3.0 picks up the same content in CCS 20.3.0, I'll need to check this.

0 Huey Duong 9 hours ago in reply to Ki

Intellectual 370 points

ok, just happened again. Power cycle board, tried programming SBL,appimage using 9.2, fails after a few blocks have been written (expected behavior from the gui. Typically loading images again works). Closed 9.2, opened 9.3, power cycled board, loaded the same images, and it hung here for 1 minute

then hung here permanently.

power cycled board and tried loading again, still stuck at same spot.

Pressed cancel and did a memory read.

Seems to get bass the RTI issue but still unable to do a proper read.

here's the log

Fullscreen 4503.log.txt Download

[9/29/2025, 1:35:43 PM] [INFO] Cortex_R5_0: GEL Output: Gel files loading Complete
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. Please Wait...
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: Crystal Clock present
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: SOP MODE = 0x00000003
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: OSPI (8S) - Octal Read Mode
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 DualCore Reset ***
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS1 DualCore Reset ***
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5F ROM Eclipse
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_0 Released
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_1 Released
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_0 Released
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_1 Released
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: L2 Mem Init Complete
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: MailBox Mem Init Complete
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: Configure all Peripheral clocks()
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks ***
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
[9/29/2025, 1:45:08 PM] [ERROR] Cortex_R5_0: GEL: Error while executing OnTargetConnect(): Target failed to read 0x53208414 at (Read_MMR((0x53208000U+0x00000414U))!=0x4) [AM263Px_Periheral_Clocks.gel:467] at Program_RTI0_Clocks() [AM263Px.gel:192] at Configure_All_Peripheral_Clks() [AM263Px.gel:100] at OnTargetConnect()
[9/29/2025, 1:45:08 PM] [INFO] Cortex_R5_0: AM263Px
[9/29/2025, 1:45:08 PM] [INFO] Cortex_R5_0: Board Selected : CC
[9/29/2025, 1:45:08 PM] [INFO] Cortex_R5_0: Part Selected : Standard
[9/29/2025, 1:45:08 PM] [ERROR] Cortex_R5_0: Error: (Error -1170 @ 0x53208414) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 20.3.0.3656)
[9/29/2025, 1:45:08 PM] [ERROR] Cortex_R5_0: Error: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 20.3.0.3656)
[9/29/2025, 1:45:09 PM] [ERROR] Cortex_R5_0: Unable to determine target status after 20 attempts
[9/29/2025, 1:45:09 PM] [ERROR] Cortex_R5_0: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. Please Wait...
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: Crystal Clock present
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: SOP MODE = 0x00000003
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: OSPI (8S) - Octal Read Mode
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 DualCore Reset ***
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS1 DualCore Reset ***
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: R5F ROM Eclipse
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_0 Released
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_1 Released
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_0 Released
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_1 Released
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: L2 Mem Init Complete
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: MailBox Mem Init Complete
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: Configure all Peripheral clocks()
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks ***
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
[9/29/2025, 1:45:42 PM] [ERROR] Cortex_R5_0: GEL: Error while executing OnTargetConnect(): Could not read 0x53208414: target is not connected at (Read_MMR((0x53208000U+0x00000414U))!=0x4) [AM263Px_Periheral_Clocks.gel:467] at Program_RTI0_Clocks() [AM263Px.gel:192] at Configure_All_Peripheral_Clks() [AM263Px.gel:100] at OnTargetConnect()
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. Please Wait...
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Crystal Clock present
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: SOP MODE = 0x00000003
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: OSPI (8S) - Octal Read Mode
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 DualCore Reset ***
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS1 DualCore Reset ***
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5F ROM Eclipse
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_0 Released
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_1 Released
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_0 Released
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_1 Released
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: L2 Mem Init Complete
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MailBox Mem Init Complete
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Configure all Peripheral clocks()
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks ***
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: RTI0 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: RTI1 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: RTI2 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: RTI3 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: WDT0 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: WDT1 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: WDT2 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: WDT3 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: LIN0_UART0 Clock Enabled (160MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: LIN1_UART1 Clock Enabled (160MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: LIN2_UART2 Clock Enabled (160MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: LIN3_UART3 Clock Enabled (160MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: LIN4_UART4 Clock Enabled (160MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: LIN5_UART5 Clock Enabled (160MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling OSPI Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: OSPI0 Clock Enabled (133MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling I2C Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: I2C Clock Enabled (48MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling TRACE Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Trace Clock Enabled (250MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCAN0 Clock Enabled (80MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCAN1 Clock Enabled (80MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCAN2 Clock Enabled (80MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCAN3 Clock Enabled (80MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MMCSD Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MMCSD Clock Enabled (48MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI0 Clock Enabled (48MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI1 Clock Enabled (48MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI2 Clock Enabled (48MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI3 Clock Enabled (48MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI4 Clock Enabled (48MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: CONTROLSS Clock Enabled (400MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling CPTS Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: CPTS Clock Enabled (250MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: RGMII5 Clock Enabled (5MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: RGMII50 Clock Enabled (50MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: RGMII250 Clock Enabled (250MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: TEMPSENSE Clock Enabled (32KHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: XTAL_MMC Clock Enabled (32KHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: ***All IP Clocks are Enabled***
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. Please Wait...
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Crystal Clock present
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: SOP MODE = 0x00000003
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: OSPI (8S) - Octal Read Mode
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 DualCore Reset ***
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS1 DualCore Reset ***
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5F ROM Eclipse
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_0 Released
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_1 Released
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_0 Released
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_1 Released
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: L2 Mem Init Complete
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MailBox Mem Init Complete
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Configure all Peripheral clocks()
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks ***
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: RTI0 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: RTI1 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: RTI2 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: RTI3 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: WDT0 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: WDT1 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: WDT2 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: WDT3 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: LIN0_UART0 Clock Enabled (160MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: LIN1_UART1 Clock Enabled (160MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: LIN2_UART2 Clock Enabled (160MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: LIN3_UART3 Clock Enabled (160MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: LIN4_UART4 Clock Enabled (160MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: LIN5_UART5 Clock Enabled (160MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling OSPI Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: OSPI0 Clock Enabled (133MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling I2C Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: I2C Clock Enabled (48MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling TRACE Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Trace Clock Enabled (250MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCAN0 Clock Enabled (80MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCAN1 Clock Enabled (80MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCAN2 Clock Enabled (80MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCAN3 Clock Enabled (80MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MMCSD Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MMCSD Clock Enabled (48MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI0 Clock Enabled (48MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI1 Clock Enabled (48MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI2 Clock Enabled (48MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI3 Clock Enabled (48MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI4 Clock Enabled (48MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: CONTROLSS Clock Enabled (400MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling CPTS Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: CPTS Clock Enabled (250MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: RGMII5 Clock Enabled (5MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: RGMII50 Clock Enabled (50MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: RGMII250 Clock Enabled (250MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: TEMPSENSE Clock Enabled (32KHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: XTAL_MMC Clock Enabled (32KHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: ***All IP Clocks are Enabled***

clicking refresh causes it be stuck again

Closed uniflash, reconnect, power cycle, load program and still stuck at Enable RTI Clocks.

Cancel, closed uniflash and ran fsclean.bat

Started uniflash again, connect, no power cycle, and load program again and it worked.

[9/29/2025, 1:52:50 PM] [INFO] Cortex_R5_0: GEL Output: Gel files loading Complete
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. Please Wait...
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Crystal Clock present
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: SOP MODE = 0x00000003
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: OSPI (8S) - Octal Read Mode
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 DualCore Reset ***
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS1 DualCore Reset ***
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: R5F ROM Eclipse
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_0 Released
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_1 Released
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_0 Released
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_1 Released
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: L2 Mem Init Complete
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: MailBox Mem Init Complete
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Configure all Peripheral clocks()
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks ***
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: RTI0 Clock Enabled (200MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: RTI1 Clock Enabled (200MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: RTI2 Clock Enabled (200MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: RTI3 Clock Enabled (200MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: WDT0 Clock Enabled (200MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: WDT1 Clock Enabled (200MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: WDT2 Clock Enabled (200MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: WDT3 Clock Enabled (200MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: LIN0_UART0 Clock Enabled (160MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: LIN1_UART1 Clock Enabled (160MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: LIN2_UART2 Clock Enabled (160MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: LIN3_UART3 Clock Enabled (160MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: LIN4_UART4 Clock Enabled (160MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: LIN5_UART5 Clock Enabled (160MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Enabling OSPI Clocks
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: OSPI0 Clock Enabled (133MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Enabling I2C Clocks
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: I2C Clock Enabled (48MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Enabling TRACE Clocks
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Trace Clock Enabled (250MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: MCAN0 Clock Enabled (80MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: MCAN1 Clock Enabled (80MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: MCAN2 Clock Enabled (80MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: MCAN3 Clock Enabled (80MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MMCSD Clocks
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: MMCSD Clock Enabled (48MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI0 Clock Enabled (48MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI1 Clock Enabled (48MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI2 Clock Enabled (48MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI3 Clock Enabled (48MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI4 Clock Enabled (48MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: CONTROLSS Clock Enabled (400MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Enabling CPTS Clocks
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: CPTS Clock Enabled (250MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: RGMII5 Clock Enabled (5MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: RGMII50 Clock Enabled (50MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: RGMII250 Clock Enabled (250MHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: TEMPSENSE Clock Enabled (32KHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: XTAL_MMC Clock Enabled (32KHz)
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: ***All IP Clocks are Enabled***
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: AM263Px
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: Board Selected : CC
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: Part Selected : Standard
[9/29/2025, 1:53:20 PM] [INFO] Cortex_R5_0: GEL Output: CPU reset (soft reset) has been issued through GEL on program load.
[9/29/2025, 1:53:23 PM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x0
[9/29/2025, 1:53:31 PM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x81000
[9/29/2025, 1:53:38 PM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x300000
[9/29/2025, 1:53:49 PM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x500000
[9/29/2025, 1:53:50 PM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x700000
[9/29/2025, 1:53:53 PM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x900000
[9/29/2025, 1:53:56 PM] [SUCCESS] Program Load completed successfully.

Arm-based microcontrollers

Arm-based microcontrollers forum

UNIFLASH: Stuck at "GEL Expression: OnTargetConnect()" or "Enabling RTI[0:3] Clocks" when loading