Hi Harishkumar,

We have provided several examples in the SDK, you can download here MSPM0-SDK .

And you can find the Lin demo in the following path: Your SDK download folder\mspm0_sdk_xxxx\examples\nortos\LP_MSPM0G3507\lin

Best Regards,
Peter

Hi Peter,

Thanks for your quick feedback. 

I have one last question, In the pins i see we have LIN TX and LIN RX and i am simulating to transmit frames from a tool called CANoe which has single LIN Line as LIN is single wire protocol.

How to connect this to the board LIN?

I am trying to see run the LIN responder code

Our board does not have a transceiver, is it? we need an external transceiver to interface with our TX/RX 

Yes, there is no Lin transceiver on the EVM board and need a external Lin transceiver to do the Lin communication.

Best Regards,
Peter

Hi Peter, Thanks for your response.

I saw the sample code but i still didn't see a LIN stack driver provided.

Do you have any driver code already written which can be adapted by us for our application or we have to develop one from scratch?

Hi Harishkumar,

Lin's implementation is based on the UART, all the Lin API is included in the "dl_uart_extend.h".

There is no separate Lin driver provided, you can refer to the demo code to encapsulate LIN RX and TX functions.

Best Regards,
Peter

Hi Peter, Thanks for your feedback. Is there any API to put the system in sleep or low power mode

Hi Harishkumar,

You can refer to the low power related demo code in the SDK. "Your SDK Download Folder\mspm0_sdk_XXXX\examples\nortos\LP_MSPM0G3507\driverlib"

Best Regards,
Peter

Hi Peter,

thanks for the information shared.

Is there any way to connect an external LIN transceiver to the TI demo board? if yes, how and if not, is there anything TI providing from their side to get the transceiver connected to the demo board

Hi Harishkumar,

Let me take TLIN1024-Q1 which is a Lin Transceiver from TI as an example, and you can also find the EVM design TLIN2029EVM of this device, so we need two launchpads and two LIN Transceivers to evaluate our demo. The two LIN transceivers only need to be connected by a single LIN communication line, and then each transceiver is connected to the corresponding Launchpad's LIN interface RX and TX respectively. 

Best Regards,
Peter

Hi Peter, my code runs into NMI handler as soon i enter debug mode and i attach you my .sct and .s file for my MSPM0G3106 mcu

startup file 
;//*****************************************************************************
;//
;// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
;//
;// Redistribution and use in source and binary forms, with or without
;// modification, are permitted provided that the following conditions
;// are met:
;//
;//  Redistributions of source code must retain the above copyright
;//  notice, this list of conditions and the following disclaimer.
;//
;//  Redistributions in binary form must reproduce the above copyright
;//  notice, this list of conditions and the following disclaimer in the
;//  documentation and/or other materials provided with the
;//  distribution.
;//
;//  Neither the name of Texas Instruments Incorporated nor the names of
;//  its contributors may be used to endorse or promote products derived
;//  from this software without specific prior written permission.
;//
;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;//
;// MSPM0G3507 startup file
;//
;//****************************************************************************
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/

; <h> Stack Configuration
;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Stack_Size      EQU     0x00000100

                AREA    STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem       SPACE   Stack_Size
__initial_sp


; <h> Heap Configuration
;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Heap_Size       EQU     0x00000000

                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem        SPACE   Heap_Size
__heap_limit


                PRESERVE8
                THUMB


; Vector Table Mapped to Address 0 at Reset

                AREA    RESET, DATA, READONLY
                EXPORT  __Vectors
                EXPORT  __Vectors_End
                EXPORT  __Vectors_Size

__Vectors       DCD     __initial_sp              ; Top of Stack
                DCD     Reset_Handler             ; Reset Handler
                DCD     NMI_Handler               ; NMI Handler
                DCD     HardFault_Handler         ; Hard Fault Handler
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     SVC_Handler               ; SVCall Handler
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     PendSV_Handler            ; PendSV Handler
                DCD     SysTick_Handler           ; SysTick Handler

                ; External Interrupts
                DCD     GROUP0_IRQHandler         ;  1:  GROUP0 interrupt handler
                DCD     GROUP1_IRQHandler         ;  2:  GROUP1 interrupt handler
                DCD     TIMG8_IRQHandler          ;  3:  TIMG8 interrupt handler
                DCD     UART3_IRQHandler          ;  4:  UART3 interrupt handler
                DCD     ADC0_IRQHandler           ;  5:  ADC0 interrupt handler
                DCD     ADC1_IRQHandler           ;  6:  ADC1 interrupt handler
                DCD     CANFD0_IRQHandler         ;  7:  CANFD0 interrupt handler
                DCD     0                         ;  8:  Reserved
                DCD     0                         ;  9:  Reserved
                DCD     SPI0_IRQHandler           ; 10:  SPI0 interrupt handler
                DCD     SPI1_IRQHandler           ; 11:  SPI1 interrupt handler
                DCD     0                         ; 12:  Reserved
                DCD     0                         ; 13:  Reserved
                DCD     UART1_IRQHandler          ; 14:  UART1 interrupt handler
                DCD     UART2_IRQHandler          ; 15:  UART2 interrupt handler
                DCD     UART0_IRQHandler          ; 16:  UART0 interrupt handler
                DCD     TIMG0_IRQHandler          ; 17:  TIMG0 interrupt handler
                DCD     TIMG6_IRQHandler          ; 18:  TIMG6 interrupt handler
                DCD     TIMA0_IRQHandler          ; 19:  TIMA0 interrupt handler
                DCD     TIMA1_IRQHandler          ; 20:  TIMA1 interrupt handler
                DCD     TIMG7_IRQHandler          ; 21:  TIMG7 interrupt handler
                DCD     TIMG12_IRQHandler         ; 22:  TIMG12 interrupt handler
                DCD     0                         ; 23:  Reserved
                DCD     0                         ; 24:  Reserved
                DCD     I2C0_IRQHandler           ; 25:  I2C0 interrupt handler
                DCD     I2C1_IRQHandler           ; 26:  I2C1 interrupt handler
                DCD     0                         ; 27:  Reserved
                DCD     0                         ; 28:  Reserved
                DCD     AES_IRQHandler            ; 29:  AES interrupt handler
                DCD     0                         ; 30:  Reserved
                DCD     RTC_IRQHandler            ; 31:  RTC interrupt handler
                DCD     DMA_IRQHandler            ; 32:  DMA interrupt handler

__Vectors_End

__Vectors_Size  EQU     __Vectors_End - __Vectors

                AREA    |.text|, CODE, READONLY


; Reset Handler

Reset_Handler   PROC
                EXPORT  Reset_Handler             [WEAK]
                ;IMPORT  SystemInit
                IMPORT  __main
				; SystemInit can be called here, but not necessary for MSPM0
                ;LDR     R0, =SystemInit
                ;BLX     R0
                LDR     R0, =__main
                BX      R0
                ENDP


; Dummy Exception Handlers (infinite loops which can be modified)

NMI_Handler     PROC
                EXPORT  NMI_Handler               [WEAK]
                B       .
                ENDP
HardFault_Handler\
                PROC
                EXPORT  HardFault_Handler         [WEAK]
                B       .
                ENDP
SVC_Handler     PROC
                EXPORT  SVC_Handler               [WEAK]
                B       .
                ENDP
PendSV_Handler  PROC
                EXPORT  PendSV_Handler            [WEAK]
                B       .
                ENDP
SysTick_Handler PROC
                EXPORT  SysTick_Handler           [WEAK]
                B       .
                ENDP

Default_Handler PROC
                EXPORT  Default_Handler           [WEAK]
				EXPORT  GROUP0_IRQHandler         [WEAK]
                EXPORT  GROUP1_IRQHandler         [WEAK]
                EXPORT  TIMG8_IRQHandler          [WEAK]
                EXPORT  UART3_IRQHandler          [WEAK]
                EXPORT  ADC0_IRQHandler           [WEAK]
                EXPORT  ADC1_IRQHandler           [WEAK]
                EXPORT  CANFD0_IRQHandler         [WEAK]
                EXPORT  SPI0_IRQHandler           [WEAK]
                EXPORT  SPI1_IRQHandler           [WEAK]
                EXPORT  UART1_IRQHandler          [WEAK]
                EXPORT  UART2_IRQHandler          [WEAK]
                EXPORT  UART0_IRQHandler          [WEAK]
                EXPORT  TIMG0_IRQHandler          [WEAK]
                EXPORT  TIMG6_IRQHandler          [WEAK]
                EXPORT  TIMA0_IRQHandler          [WEAK]
                EXPORT  TIMA1_IRQHandler          [WEAK]
                EXPORT  TIMG7_IRQHandler          [WEAK]
                EXPORT  TIMG12_IRQHandler         [WEAK]
                EXPORT  I2C0_IRQHandler           [WEAK]
                EXPORT  I2C1_IRQHandler           [WEAK]
                EXPORT  AES_IRQHandler            [WEAK]
                EXPORT  RTC_IRQHandler            [WEAK]
                EXPORT  DMA_IRQHandler            [WEAK]

GROUP0_IRQHandler
GROUP1_IRQHandler
TIMG8_IRQHandler
UART3_IRQHandler
ADC0_IRQHandler
ADC1_IRQHandler
CANFD0_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART0_IRQHandler
TIMG0_IRQHandler
TIMG6_IRQHandler
TIMA0_IRQHandler
TIMA1_IRQHandler
TIMG7_IRQHandler
TIMG12_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
AES_IRQHandler
RTC_IRQHandler
DMA_IRQHandler
                B       .
                ENDP

                ALIGN


; User Initial Stack & Heap

                IF      :DEF:__MICROLIB

                EXPORT  __initial_sp
                EXPORT  __heap_base
                EXPORT  __heap_limit

                ELSE

                IMPORT  __use_two_region_memory
                EXPORT  __user_initial_stackheap

__user_initial_stackheap PROC
                LDR     R0, =  Heap_Mem
                LDR     R1, =(Stack_Mem + Stack_Size)
                LDR     R2, = (Heap_Mem +  Heap_Size)
                LDR     R3, = Stack_Mem
                BX      LR
                ENDP

                ALIGN

                ENDIF


                END
 and 
 
 
 scatter file 
 
 /*****************************************************************************

  Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ 

  Redistribution and use in source and binary forms, with or without 
  modification, are permitted provided that the following conditions 
  are met:

   Redistributions of source code must retain the above copyright 
   notice, this list of conditions and the following disclaimer.

   Redistributions in binary form must reproduce the above copyright
   notice, this list of conditions and the following disclaimer in the 
   documentation and/or other materials provided with the   
   distribution.

   Neither the name of Texas Instruments Incorporated nor the names of
   its contributors may be used to endorse or promote products derived
   from this software without specific prior written permission.

  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

*****************************************************************************/
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************

LR_IROM1 0x00000000 0x00010000  {    ; load region size_region
  ER_IROM1 0x00000000 ALIGNALL 8 0x00010000  {  ; load address = execution address
   *.o (RESET, +First)
   *(InRoot$$Sections)
   .ANY (+RO)
   .ANY (+XO)
  }
  RW_IRAM2 0x20200000 0x00008000  {  ; RW data
   .ANY (+RW +ZI)
   .ANY (.ramfunc)
  }
}

LR_BCR 0x41C00000 0x00000100  {    ; load region size_region
  BCR_CONFIG 0x41C00000 0x000000FF{
	.ANY (.BCRConfig)
  }
}

LR_BSL 0x41C00100 0x00000100  {    ; load region size_region
   BSL_CONFIG 0x41C00100 0x00000080{
	.ANY (.BSLConfig)
  }
}
 what might be the reason 

GETTING THIS IN 0x00000000.

Can you please help me to fix this issue? 

Hi Harishkumar,

If you can confirm it always enter into the NMI, then I believe you can check the following causes of NMI one by one in your code to locate the root cause.

Best Regards,
Peter

Hi Peter,

My LIN handler is not being called when i transmit frames on the bus. i can see the LIN Enable to be high, and i have also configured LIN TX and RX as well.

But when i send frames in my bus i don't see my handler being called.

please help me to solve this problem as this is a blocker

int main( void )
{
	  SYSCFG_DL_init();
	  NVIC_ClearPendingIRQ(LIN_0_INST_INT_IRQN);
    NVIC_EnableIRQ(LIN_0_INST_INT_IRQN);	  

		
		while (1) {
        __WFI();
    }

	return 1;
}

SYSCONFIG_WEAK void SYSCFG_DL_init(void)
{
    SYSCFG_DL_initPower();
    SYSCFG_DL_GPIO_init();
    /* Module-Specific Initializations*/
    SYSCFG_DL_SYSCTL_init();
}

SYSCONFIG_WEAK void SYSCFG_DL_initPower(void)
{
    DL_GPIO_reset(GPIOA);
	  DL_GPIO_reset(GPIOB);
    DL_UART_Extend_reset(LIN_0_INST);
    DL_GPIO_enablePower(GPIOA);
	  DL_GPIO_enablePower(GPIOB);
    DL_UART_Extend_enablePower(LIN_0_INST);
    delay_cycles(POWER_STARTUP_DELAY);
}

SYSCONFIG_WEAK void SYSCFG_DL_GPIO_init(void)
{

    DL_GPIO_initPeripheralOutputFunction(
        GPIO_LIN_0_IOMUX_TX, GPIO_LIN_0_IOMUX_TX_FUNC);
    DL_GPIO_initPeripheralInputFunction(
        GPIO_LIN_0_IOMUX_RX, GPIO_LIN_0_IOMUX_RX_FUNC);
		DL_GPIO_initDigitalOutput(IOMUX_PINCM24);
		DL_GPIO_clearPins(GPIOB, GPIO_LIN_ENABLE_USER_LIN_ENABLE_PIN);
		DL_GPIO_enableOutput(GPIOB, GPIO_LIN_ENABLE_USER_LIN_ENABLE_PIN);

}
SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_init(void)
{

	//Low Power Mode is configured to be SLEEP0
    DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);

    
	DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
	/* Set default configuration */
	DL_SYSCTL_disableHFXT();
	DL_SYSCTL_disableSYSPLL();

}

static const DL_UART_Extend_ClockConfig gLIN_0ClockConfig = {
    .clockSel    = DL_UART_EXTEND_CLOCK_BUSCLK,
    .divideRatio = DL_UART_EXTEND_CLOCK_DIVIDE_RATIO_1
};

static const DL_UART_Extend_Config gLIN_0Config = {
    .mode        = DL_UART_EXTEND_MODE_NORMAL,
    .direction   = DL_UART_EXTEND_DIRECTION_TX_RX,
    .flowControl = DL_UART_EXTEND_FLOW_CONTROL_NONE,
    .parity      = DL_UART_EXTEND_PARITY_NONE,
    .wordLength  = DL_UART_EXTEND_WORD_LENGTH_8_BITS,
    .stopBits    = DL_UART_EXTEND_STOP_BITS_ONE
};

SYSCONFIG_WEAK void SYSCFG_DL_LIN_0_init(void)
{
    DL_UART_Extend_setClockConfig(LIN_0_INST, (DL_UART_Extend_ClockConfig *) &gLIN_0ClockConfig);

    DL_UART_Extend_init(LIN_0_INST, (DL_UART_Extend_Config *) &gLIN_0Config);
    /*
     * Configure baud rate by setting oversampling and baud rate divisors.
     *  Target baud rate: 19200
     *  Actual baud rate: 19200.77
     */
    DL_UART_Extend_setOversampling(LIN_0_INST, DL_UART_OVERSAMPLING_RATE_16X);
    DL_UART_Extend_setBaudRateDivisor(LIN_0_INST, LIN_0_IBRD_40_MHZ_19200_BAUD, LIN_0_FBRD_40_MHZ_19200_BAUD);


    /* Configure Interrupts */
    DL_UART_Extend_enableInterrupt(LIN_0_INST,
                                 DL_UART_EXTEND_INTERRUPT_BREAK_ERROR |
                                 DL_UART_EXTEND_INTERRUPT_LINC0_MATCH |
                                 DL_UART_EXTEND_INTERRUPT_LIN_COUNTER_OVERFLOW |
                                 DL_UART_EXTEND_INTERRUPT_LIN_FALLING_EDGE|
                                 DL_UART_EXTEND_INTERRUPT_RXD_POS_EDGE);
	
    /* Setting the Interrupt Priority */
    NVIC_SetPriority(LIN_0_INST_INT_IRQN, 1);


    /* Configure LIN settings */
    DL_UART_Extend_enableLINCounter(LIN_0_INST);
    DL_UART_Extend_setLINCounterValue(LIN_0_INST, 0);
    DL_UART_Extend_enableLINCounterCompareMatch(LIN_0_INST);
    DL_UART_Extend_setLINCounterCompareValue(LIN_0_INST, LIN_0_COUNTER_COMPARE_VALUE);
    DL_UART_Extend_enableLINCountWhileLow(LIN_0_INST);
    DL_UART_Extend_enableLINCounterClearOnFallingEdge(LIN_0_INST);

    DL_UART_Extend_enable(LIN_0_INST);
}

/* clang-format off */

#define POWER_STARTUP_DELAY                                                (16)



#define CPUCLK_FREQ                                                     80000000

/* Defines for LIN_0 */
#define LIN_0_INST                                                         UART0
#define LIN_0_INST_IRQHandler                                   UART0_IRQHandler
#define LIN_0_INST_INT_IRQN                                       UART0_INT_IRQn
#define GPIO_LIN_0_RX_PORT                                                 GPIOA
#define GPIO_LIN_0_TX_PORT                                                 GPIOA
#define GPIO_LIN_0_RX_PIN                                          DL_GPIO_PIN_11
#define GPIO_LIN_0_TX_PIN                                          DL_GPIO_PIN_10
#define GPIO_LIN_0_IOMUX_RX                                       (IOMUX_PINCM22)
#define GPIO_LIN_0_IOMUX_TX                                       (IOMUX_PINCM21)
#define GPIO_LIN_0_IOMUX_RX_FUNC                        IOMUX_PINCM22_PF_UART0_RX
#define GPIO_LIN_0_IOMUX_TX_FUNC                        IOMUX_PINCM21_PF_UART0_TX
#define LIN_0_BAUD_RATE                                                  (19200)
#define LIN_0_IBRD_40_MHZ_19200_BAUD                                       (130)
#define LIN_0_FBRD_40_MHZ_19200_BAUD                                        (13)
#define LIN_0_TBIT_WIDTH                                                  (2083)
#define LIN_0_TBIT_COUNTER_COEFFICIENT                                     (9.5)
#define LIN_0_COUNTER_COMPARE_VALUE                                      (19792)
/* Port definition for Pin Group GPIO_LIN_ENABLE */
#define GPIO_LIN_ENABLE_PORT                                             (GPIOB)
/* Port definition for Pin Group GPIO */
#define GPIO_PORT                                                        (GPIOA)

/* Defines for USER_LIN_ENABLE: GPIOB.15 with pinCMx 32 on package pin 3 */
#define GPIO_LIN_ENABLE_USER_LIN_ENABLE_PIN                     (DL_GPIO_PIN_7)
#define GPIO_LIN_ENABLE_USER_LIN_ENABLE_IOMUX                    (IOMUX_PINCM24)

Hi Harishkumar,

I don't see any suspicious in the code so far, please ensure that the hardware connection is stable and good, or you can just firstly use the sdk responder demo to test first to see whether it can enter into the handler or not, try to rule out some hardware setting and testing issues.

Best Regards,

Peter

Hi Peter,

Thanks for your feedback.

Here what i would like to highlight is this code is for MSPM0G3106 and also, we see the voltage level out of our transceiver to MCU is between 3.3 and 2.6 and not close to 0V and we see in the MCU we have 

UART TX / RX and BSLTX / BSLRX functions are Multiplexed to PA10, PA11. Can they affect Voltage levels if something not configured properly in SW?

If yes, what can be the possible SW configuration issue?

Hi Peter,

I was able to resolve the issue.

It was the pull up missing in RX.

My code is throwing invalid ROM table error when trying to flash or enter debug and i tried connecting under reset with HW reset, system reset etc.., but nothing worked.

I Tried segger but that also blocks me from erasing chip and i dont have XDS debugger port on my PCBA.

My watchdog is halting the core restarting fast and i am unable to enter.

How to mass erase the chip ?

Please provide me some help here

Hi Harishkumar,

I noticed that you have brought out the BSL invoke pin PA18, right? please refer to the following steps MSPM0 MCUs Development Guide (Rev. G) , first enter into the BSL, and then try to do the factory reset or mass erase.

Step1:

Step2:

Best Regards,
Peter

Hi Peter,

Is there anything that can be done with Keil and JLINK or ULINK?

Because I don't have the XDS debugger with me and also i don't have CCS with me (But i can install CCS but i dont have a XDS Debugger)?

 I see press the reset button there. does that mean holding NRST Pin High?

In the manual, you shared i see every method uses XDS debugger.

Is there anything that can be done with JLINK OR ULINK ?

how does the bootloader work? does it use XDS debugger or with Some UART connections from PC?

Hi Harishkumar,

Could you please take a look at this thread MSPM0L1305: DSSM commands to Factory reset without XDS110 to have a try by using JLINK to do the factory reset?

Best Regards,
Peter

Hi Peter,

The problem is my watchdog is enabled, and it is resetting very fast due to missed service and also it is configured such that it halts core during debug phase.

Due to this WDT is continuously resetting the mcu and during this reset, it is continuously halting the core and due to this SWD is not accessible for me and i am unable to flash the file or enter debug mode

and if i try the script given in the other thread you shared. i am getting the following error,

Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: Core did not halt after reset, trying to disable WDT.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: CPU did not halt after reset.
Reset: Using fallback: Reset pin.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Found SW-DP with ID 0x6BA02477
DPIDR: 0x6BA02477
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Skipped. Invalid implementer code read from CPUIDVal[31:24] = 0x00
Reset: Core is locked-up, trying to disable WDT.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Found SW-DP with ID 0x6BA02477
DPIDR: 0x6BA02477
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xF0000000
CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)
Found Cortex-M0 r0p1, Little endian.

****** Error: Could not find core in Coresight setup

where i can also see Reset: Core did not halt after reset, trying to disable WDT,

so how can i disable this watchdog behavior and continue to enter debug mode and make flashing of new .hex files.

Please guide me further.

Hi Harishkumar,

The thread that I share to you is the process of doing the factory reset, since you enable the watchdog, still need to enter into the BSL first and it will stuck in our ROM BSL code for 10 seconds, so you can try to do the factory reset by JLINK within this 10 seconds and see whether it can solve the problem.

Best Regards,
Peter

for enabling BSL, just setting BSL Invoke is high is enough, right?

Yes, make sure BSL invoke pin is high once power on, you can connect the PA18 invoke pin to the VCC first, and then re-power on the device.

Hi Peter,

The BSL invoke was not powered and my JLINK was connected to the SWIO, SWCLK ports and i enable 3.3V for BSL invoke and then performed a POR and i ran the script but i am getting still the same watchdog error

Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: Core did not halt after reset, trying to disable WDT.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: CPU did not halt after reset.
Reset: Using fallback: Reset pin.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Found SW-DP with ID 0x6BA02477
DPIDR: 0x6BA02477
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xF0000000
CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)
Found Cortex-M0 r0p1, Little endian.

You didn't modify the BSL invoke pin in the Nonmain manually and use the default PA18 as the BSL invoke pin, right?

Do you connect the NRST pin except for the SWDCLK/SWDIO, if not, you can connect it and try again.

and have you got another normal board without watchdog enabled, if so you can try the script in that board to see whether the script's factory reset works.

In the flashed SW which is struck in the board i have configured UART0 TX and RX for PA 10, 11 but havent configured anything for PA18.

The NRST pin is connected to Segger's Rst pin.

I have powered Vcc to the BSL invoke pin and ground is also connected. But not connected BSL TX and RX.

Also, i will try with the other board. But why my code is not entering BSL for 10 seconds because i can see the system reset being called at the scripts where it is getting failed because core not halted due to Watchdog.

Hi Peter, is the sequence and steps i gave above correct?

Also since watchdog is the one causing the issue is there any way to turn off Watchdog that causes this issue by writing into register memory?

If not please tell me the steps with which i should execute the JLINK script you shared in the other thread

Hi Peter, any feedback here. I can confirm you it is the watchdog that is stopping the reset sequence at the beginning of JLINK script you shared which is preventing the factory reset. Can you please provide me a solution to perform the factory reset to disable to watchdog which is configured so fast and halting the core

Hi Peter, The sequence you said worked. Thanks for your help. 

Hi Harishkumar,

You're welcome, glad to hear that the issue has been solved, since that, I will close this thread.

Best Regards,
Peter