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MSPM0G3107: Controller area network module sending unexpected DATA on bus

Rohit Nagare
Prodigy 20 points

Part Number: MSPM0G3107
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hello all,
I am getting unusual data mismatch in CAN module of MSPM0G3107: so basically I am sending one can message with specific periodicity of 215 MS on can bus with fixed data from the compile time of firmware and it is not changed by application software in runtime it's just send on bus periodically but I am getting random jump in data after some interval which is also not fixed. I am sending same data on UART to serial monitor but the data recieved there is exactly as expected, is it the issue with MCAN RAM, but only fraction od entire packet is mismatched rest of ID's and other bytes in frame seems to be fine.
I am getting this issue only where another device is transfering data on bus and my RX interrupt is triggered and it's made sure that no-one else is send the data with this same ID so message is only sent from my device.
I am using polling to send the data using TX buffers rather than FIFOs and there's no RTOS for this project it's super loop with scheduled time.
My MCAN settings are as follows:
Bit rate : 500 KbPs,
Clock Source : SYSPLLCLK1
MCAN ClK freq: 40MHZ with divider 1
SYSOSC(internal osillator) : 32 MHz
Below are the log files for the same signals.

  • 0 in reply to Rohit Nagare
    TI__Mastermind 29895 points

    Hi Rohit,

    I haven't meet this kind of situation.

    I suggest you check the CAN buffer setting and CAN Tx message variable, continously observe it in debug mode to see any abnormal situation.

    B.R.

    Sal

  • 0 in reply to Sal Ye
    Prodigy 20 points

    any perticular area to focus on while checking the CAN buffer settings?, I can not continously monitor variables in debug mode as it is stated in refrence manual that this controller behaves differently in debug mode. also could it be case that Tx buffer and Rx buffer inside the CAN peripheral might be overlaping? cause this issue only occurs when there's another unit transmitting data on the bus which is received by my device.

  • 0 in reply to Rohit Nagare
    TI__Mastermind 29895 points

    Hi Rohit,

    It worth a try to check any difference in debug mode or free run mode.

    Rohit Nagare said:
    also could it be case that Tx buffer and Rx buffer inside the CAN peripheral might be overlaping?

    You can check the message RAM setting, to see if there has memory overlap.

    Maybe you can share you message RAM map here and I can double check.

    Rohit Nagare said:
    but only fraction od entire packet is mismatched rest of ID's and other bytes in frame seems to be fine.

    Is the incorrect packege fixed or it is a random packet with incorrect data?

    B.R.

    Sal

  • 0 in reply to Sal Ye
    Prodigy 20 points
    Sal Ye said:

    Is the incorrect packege fixed or it is a random packet with incorrect data?

    well the packets CAN ID (std) is correct but the DLC and the data in it is incorrect but the CRC which is calculated at the physical layer seems fine cause if that would be mismatching the packet would have been discarded at the physical layer of CAN.


    Sal Ye said:

    You can check the message RAM setting, to see if there has memory overlap.

    Sal Ye said:

    Maybe you can share you message RAM map here and I can double check.

    • TX MSG RAM
    TX Buffers Start Address 
    148
    TX Buffer Start Address 148 End Address 1012
    Number of Dedicated Transmit Buffers 
    2
    No of TX FIFO Elements 
    10
    TX FIFO Operation Mode 
    Tx Queue Operation Mode
    TX Buffer Element Size 
    64 byte data field
    TX Event FIFO Start Address 
    TX Event FIFO Start Address 164 End Address 168
    TX Event FIFO Size 
    2
    TX Event FIFO Watermark INT Level 
    0
    • RX MSG RAM
    RX FIFO0 Start Address 
    8
    RX FIFO 0 Start Address 8 End Address 368
    Number of RX FIFO0 Elements 
    5
    RX FIFO0 Watermark 
    0
    RX FIFO0 Operation Mode 
    FIFO blocking mode
    RX FIFO1 Start Address 
    368
    RX FIFO 1 Start Address 368 End Address 448
    Number of RX FIFO1 Elements 
    5
    RX FIFO1 Watermark 
    3
    RX FIFO1 Operation Mode 
    FIFO overwrite Mode
    RX Buffer Start Address 
    600
    RX Buffer Start Address 600 End Address 672
    RX Buffer Element Size 
    64 bytes
    RX FIFO0 Element Size 
    64 bytes
    RX FIFO1 Element Size 
    8 bytes

    In this I only use the TX Buffer 0 and explicitly wait for it to finish transmition on the bus, and I have made sure to get rid of all the warnings mentioning there are addresses overlapping in sysconfig.

  • 0 in reply to Rohit Nagare
    TI__Mastermind 29895 points

    Hi Rohit,

    The Tx and Rx share the same Message RAM, I do see some conflict in your sharing:

    Can you share the whole syscfg files for my reference, please also let me know your SDK and SysConfig version used.

    B.R.

    Sal

  • 0 in reply to Sal Ye
    Prodigy 20 points

    can_to_i2c_controller_bridge.rar
    Here is my syscfg file, I am using TI-ClangCompiler and sysCfg- 1.22.0 and MSP m0 SDK  is 2.4.0.06 version.
    also will enabling ECC for message RAM help me?