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TMS570LC4357: Information on peripherals for static timing analysis

pada
Prodigy 10 points
Part Number: TMS570LC4357


Tool/software:

Hi we are using abstract interpretation to analyse the Worst Case Execution Time on the TMS570CL4357 Rev B and I would like to know if there is anywhere information on the timings for the internal peripherals. 

The questions I would like to answer is i.e. how many VCLK cycles does it takes to access RTI in the Worst Case? Is there a difference between the peripherals on the same subsystem? Is there anywhere documentation for this topic?

  • 0
    TI__Guru 74376 points

    Hi Pada,

    I can provide the following information about peripheral access timing for the TMS570CL4357:

    1. For MibSPI peripheral:
    • When the SPI enable signal is not used, the MibSPI master should wait for 6 VCLK cycles before sending the SPI clock to begin a transaction
    1. For interrupt handling:
    • The interrupt latency in Hercules devices can range from 20 to 47 clock cycles
    1. For memory access:
    • TCM (Tightly Coupled Memory) and cached OCRAM have similar access latencies
    • Non-cached OCRAM has significantly higher access latency

    Regarding your specific questions:

    For RTI access timing: While the exact number of VCLK cycles for RTI access is not explicitly documented in the available sources, the RTI peripheral does have specific timing considerations for register access and counter operations.

    --
    Thanks & regards,
    Jagadish.