SYSCONFIG: Sysconfig issue to upload json file for customer flash

Jan Bock

Part Number: SYSCONFIG

Tool/software:

MAIN_Cortex_R5_0_0: [OSPI Flash Diagnostic Test] Starting ...

MAIN_Cortex_R5_0_0: [OSPI Flash Diagnostic Test] Flash Manufacturer ID : 0x20

MAIN_Cortex_R5_0_0: [OSPI Flash Diagnostic Test] Flash Device ID       : 0xBA18

MAIN_Cortex_R5_0_0: [OSPI Flash Diagnostic Test] Executing Flash Erase on first block...

MAIN_Cortex_R5_0_0: [OSPI Flash Diagnostic Test] Done !!!

MAIN_Cortex_R5_0_0: [OSPI Flash Diagnostic Test] Performing Write-Read Test...

MAIN_Cortex_R5_0_0: [OSPI Flash Diagnostic Test] Write-Read Test Passed!

MAIN_Cortex_R5_0_0: [QSPI Flash Diagnostic Test] SFDP Information : 

MAIN_Cortex_R5_0_0: ================================================

MAIN_Cortex_R5_0_0:                       SFDP                      

MAIN_Cortex_R5_0_0: ================================================

MAIN_Cortex_R5_0_0: SFDP Major Revision                       : 0x1

MAIN_Cortex_R5_0_0: SFDP Minor Revision                       : 0x6

MAIN_Cortex_R5_0_0: Number of Parameter Headers in this Table : 2

MAIN_Cortex_R5_0_0: 

MAIN_Cortex_R5_0_0: Types of Additional Parameter Tables in this flash

MAIN_Cortex_R5_0_0: ---------------------------------------------------

MAIN_Cortex_R5_0_0: 4 BYTE ADDRESSING MODE INSTRUCTIONS TABLE

MAIN_Cortex_R5_0_0: JSON Data for the flash :

MAIN_Cortex_R5_0_0: 

MAIN_Cortex_R5_0_0: {

MAIN_Cortex_R5_0_0: 

MAIN_Cortex_R5_0_0:     "flashSize": 16777216,

MAIN_Cortex_R5_0_0:     "flashPageSize": 256,

MAIN_Cortex_R5_0_0:     "flashManfId": "0x20",

MAIN_Cortex_R5_0_0:     "flashDeviceId": "0xBA18",

MAIN_Cortex_R5_0_0:     "flashBlockSize": 65536,

MAIN_Cortex_R5_0_0:     "flashSectorSize": 4096,

MAIN_Cortex_R5_0_0:     "cmdBlockErase3B": "0xD8",

MAIN_Cortex_R5_0_0:     "cmdBlockErase4B": "0xFF",

MAIN_Cortex_R5_0_0:     "cmdSectorErase3B": "0x20",

MAIN_Cortex_R5_0_0:     "cmdSectorErase4B": "0xFF",

MAIN_Cortex_R5_0_0:     "protos": {

MAIN_Cortex_R5_0_0:             "p111": {

MAIN_Cortex_R5_0_0:                     "isDtr": false,

MAIN_Cortex_R5_0_0:                     "cmdRd": "0x03",

MAIN_Cortex_R5_0_0:                     "cmdWr": "0x02",

MAIN_Cortex_R5_0_0:                     "modeClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "modeClksRd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksRd": 0,

MAIN_Cortex_R5_0_0:                     "enableType": "0",

MAIN_Cortex_R5_0_0:                     "enableSeq": "0x00",

MAIN_Cortex_R5_0_0:                     "dummyCfg": null,

MAIN_Cortex_R5_0_0:                     "protoCfg": null,

MAIN_Cortex_R5_0_0:                     "strDtrCfg": null

MAIN_Cortex_R5_0_0:             },

MAIN_Cortex_R5_0_0:             "p112": {

MAIN_Cortex_R5_0_0:                     "isDtr": false,

MAIN_Cortex_R5_0_0:                     "cmdRd": "0x3B",

MAIN_Cortex_R5_0_0:                     "cmdWr": "0x02",

MAIN_Cortex_R5_0_0:                     "modeClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "modeClksRd": 1,

MAIN_Cortex_R5_0_0:                     "dummyClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksRd": 7,

MAIN_Cortex_R5_0_0:                     "enableType": "0",

MAIN_Cortex_R5_0_0:                     "enableSeq": "0x00",

MAIN_Cortex_R5_0_0:                     "dummyCfg": null,

MAIN_Cortex_R5_0_0:                     "protoCfg": null,

MAIN_Cortex_R5_0_0:                     "strDtrCfg": null

MAIN_Cortex_R5_0_0:             },

MAIN_Cortex_R5_0_0:             "p114": {

MAIN_Cortex_R5_0_0:                     "isDtr": false,

MAIN_Cortex_R5_0_0:                     "cmdRd": "0x6B",

MAIN_Cortex_R5_0_0:                     "cmdWr": "0x02",

MAIN_Cortex_R5_0_0:                     "modeClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "modeClksRd": 1,

MAIN_Cortex_R5_0_0:                     "dummyClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksRd": 7,

MAIN_Cortex_R5_0_0:                     "enableType": "0",

MAIN_Cortex_R5_0_0:                     "enableSeq": "0x00",

MAIN_Cortex_R5_0_0:                     "dummyCfg": null,

MAIN_Cortex_R5_0_0:                     "protoCfg": null,

MAIN_Cortex_R5_0_0:                     "strDtrCfg": null

MAIN_Cortex_R5_0_0:             },

MAIN_Cortex_R5_0_0:             "p118": {

MAIN_Cortex_R5_0_0:                     "isDtr": false,

MAIN_Cortex_R5_0_0:                     "cmdRd": "0x7C",

MAIN_Cortex_R5_0_0:                     "cmdWr": "0x84",

MAIN_Cortex_R5_0_0:                     "modeClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "modeClksRd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksRd": 0,

MAIN_Cortex_R5_0_0:                     "enableType": "255",

MAIN_Cortex_R5_0_0:                     "enableSeq": "0x00",

MAIN_Cortex_R5_0_0:                     "dummyCfg": null,

MAIN_Cortex_R5_0_0:                     "protoCfg": null,

MAIN_Cortex_R5_0_0:                     "strDtrCfg": null

MAIN_Cortex_R5_0_0:             },

MAIN_Cortex_R5_0_0:             "p444s": {

MAIN_Cortex_R5_0_0:                     "isDtr": false,

MAIN_Cortex_R5_0_0:                     "cmdRd": "0xEB",

MAIN_Cortex_R5_0_0:                     "cmdWr": "0x02",

MAIN_Cortex_R5_0_0:                     "modeClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "modeClksRd": 1,

MAIN_Cortex_R5_0_0:                     "dummyClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksRd": 9,

MAIN_Cortex_R5_0_0:                     "enableType": "0",

MAIN_Cortex_R5_0_0:                     "enableSeq": "0x14",

MAIN_Cortex_R5_0_0:                     "dummyCfg": {

MAIN_Cortex_R5_0_0:                             "isAddrReg": false,

MAIN_Cortex_R5_0_0:                             "cmdRegRd":"0x00",

MAIN_Cortex_R5_0_0:                             "cmdRegWr":"0x00",

MAIN_Cortex_R5_0_0:                             "cfgReg":"0x00000000",

MAIN_Cortex_R5_0_0:                             "shift":0,

MAIN_Cortex_R5_0_0:                             "mask":"0x00",

MAIN_Cortex_R5_0_0:                             "bitP":0

MAIN_Cortex_R5_0_0:                     },

MAIN_Cortex_R5_0_0:                     "protoCfg": {

MAIN_Cortex_R5_0_0:                             "isAddrReg": false,

MAIN_Cortex_R5_0_0:                             "cmdRegRd": "0x00",

MAIN_Cortex_R5_0_0:                             "cmdRegWr": "0x00",

MAIN_Cortex_R5_0_0:                             "cfgReg": "0x00000000",

MAIN_Cortex_R5_0_0:                             "shift": 0,

MAIN_Cortex_R5_0_0:                             "mask": "0x00",

MAIN_Cortex_R5_0_0:                             "bitP": 0

MAIN_Cortex_R5_0_0:                     },

MAIN_Cortex_R5_0_0:                     "strDtrCfg": {

MAIN_Cortex_R5_0_0:                             "isAddrReg": false,

MAIN_Cortex_R5_0_0:                             "cmdRegRd": "0x00",

MAIN_Cortex_R5_0_0:                             "cmdRegWr": "0x00",

MAIN_Cortex_R5_0_0:                             "cfgReg": "0x00000000",

MAIN_Cortex_R5_0_0:                             "shift": 0,

MAIN_Cortex_R5_0_0:                             "mask": "0x00",

MAIN_Cortex_R5_0_0:                             "bitP": 0

MAIN_Cortex_R5_0_0:                     }

MAIN_Cortex_R5_0_0:             },

MAIN_Cortex_R5_0_0:             "p444d": {

MAIN_Cortex_R5_0_0:                     "isDtr": false,

MAIN_Cortex_R5_0_0:                     "cmdRd": "0xEB",

MAIN_Cortex_R5_0_0:                     "cmdWr": "0x02",

MAIN_Cortex_R5_0_0:                     "modeClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "modeClksRd": 1,

MAIN_Cortex_R5_0_0:                     "dummyClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksRd": 9,

MAIN_Cortex_R5_0_0:                     "enableType": "0",

MAIN_Cortex_R5_0_0:                     "enableSeq": "0x14",

MAIN_Cortex_R5_0_0:                     "dummyCfg": {

MAIN_Cortex_R5_0_0:                             "isAddrReg": false,

MAIN_Cortex_R5_0_0:                             "cmdRegRd":"0x00",

MAIN_Cortex_R5_0_0:                             "cmdRegWr":"0x00",

MAIN_Cortex_R5_0_0:                             "cfgReg":"0x00000000",

MAIN_Cortex_R5_0_0:                             "shift":0,

MAIN_Cortex_R5_0_0:                             "mask":"0x00",

MAIN_Cortex_R5_0_0:                             "bitP":0

MAIN_Cortex_R5_0_0:                     },

MAIN_Cortex_R5_0_0:                     "protoCfg": {

MAIN_Cortex_R5_0_0:                             "isAddrReg": false,

MAIN_Cortex_R5_0_0:                             "cmdRegRd": "0x00",

MAIN_Cortex_R5_0_0:                             "cmdRegWr": "0x00",

MAIN_Cortex_R5_0_0:                             "cfgReg": "0x00000000",

MAIN_Cortex_R5_0_0:                             "shift": 0,

MAIN_Cortex_R5_0_0:                             "mask": "0x00",

MAIN_Cortex_R5_0_0:                             "bitP": 0

MAIN_Cortex_R5_0_0:                     },

MAIN_Cortex_R5_0_0:                     "strDtrCfg": {

MAIN_Cortex_R5_0_0:                             "isAddrReg": false,

MAIN_Cortex_R5_0_0:                             "cmdRegRd": "0x00",

MAIN_Cortex_R5_0_0:                             "cmdRegWr": "0x00",

MAIN_Cortex_R5_0_0:                             "cfgReg": "0x00000000",

MAIN_Cortex_R5_0_0:                             "shift": 0,

MAIN_Cortex_R5_0_0:                             "mask": "0x00",

MAIN_Cortex_R5_0_0:                             "bitP": 0

MAIN_Cortex_R5_0_0:                     }

MAIN_Cortex_R5_0_0:             },

MAIN_Cortex_R5_0_0:             "p888s": null,

MAIN_Cortex_R5_0_0:             "p888d": null,

MAIN_Cortex_R5_0_0:             "pCustom": { 

MAIN_Cortex_R5_0_0:                     "fxn": null

MAIN_Cortex_R5_0_0:             }

MAIN_Cortex_R5_0_0:     },

MAIN_Cortex_R5_0_0:     "addrByteSupport": "0",

MAIN_Cortex_R5_0_0:     "fourByteAddrEnSeq": "0x00",

MAIN_Cortex_R5_0_0:     "cmdExtType": "NONE",

MAIN_Cortex_R5_0_0:     "resetType": "0x3D",

MAIN_Cortex_R5_0_0:     "deviceBusyType": "0",

MAIN_Cortex_R5_0_0:     "cmdWren": "0x06",

MAIN_Cortex_R5_0_0:     "cmdRdsr": "0x05",

MAIN_Cortex_R5_0_0:     "srWip":  0,

MAIN_Cortex_R5_0_0:     "srWel":  0,

MAIN_Cortex_R5_0_0:     "cmdChipErase": "0xC7",

MAIN_Cortex_R5_0_0:     "rdIdSettings": {

MAIN_Cortex_R5_0_0:             "cmd": "0x9F",

MAIN_Cortex_R5_0_0:             "numBytes": 5,

MAIN_Cortex_R5_0_0:             "dummy4": 0,

MAIN_Cortex_R5_0_0:             "dummy8": 0

MAIN_Cortex_R5_0_0:     },

MAIN_Cortex_R5_0_0:     "xspiWipRdCmd": "0x00",

MAIN_Cortex_R5_0_0:     "xspiWipReg": "0x00000000",

MAIN_Cortex_R5_0_0:     "xspiWipBit": 0,

MAIN_Cortex_R5_0_0:     "flashDeviceBusyTimeout": 40000000,

MAIN_Cortex_R5_0_0:     "flashPageProgTimeout": 120

MAIN_Cortex_R5_0_0: }

MAIN_Cortex_R5_0_0: 

MAIN_Cortex_R5_0_0: All tests have passed!!

Fullscreen QSPI_JSON_reduced.json Download

{
  "flashSize": 16777216,
  "flashPageSize": 256,
  "flashManfId": "0x20",
  "flashDeviceId": "0xBA18",
  "flashBlockSize": 65536,
  "flashSectorSize": 4096,
  "cmdBlockErase3B": "0xD8",
  "cmdBlockErase4B": "0xFF",
  "cmdSectorErase3B": "0x20",
  "cmdSectorErase4B": "0xFF",
  "protos": {
    "p111": {
      "isDtr": false,
      "cmdRd": "0x03",
      "cmdWr": "0x02",
      "modeClksCmd": 0,
      "modeClksRd": 0,
      "dummyClksCmd": 0,
      "dummyClksRd": 0,
      "enableType": "0",
      "enableSeq": "0x00",
      "dummyCfg": null,
      "protoCfg": null,
      "strDtrCfg": null
    },
    "p112": {
      "isDtr": false,
      "cmdRd": "0x3B",
      "cmdWr": "0x02",
      "modeClksCmd": 0,
      "modeClksRd": 1,
      "dummyClksCmd": 0,
      "dummyClksRd": 7,
      "enableType": "0",
      "enableSeq": "0x00",
      "dummyCfg": null,
      "protoCfg": null,
      "strDtrCfg": null
    },
    "p114": {
      "isDtr": false,
      "cmdRd": "0x6B",
      "cmdWr": "0x02",
      "modeClksCmd": 0,
      "modeClksRd": 1,
      "dummyClksCmd": 0,
      "dummyClksRd": 7,
      "enableType": "0",
      "enableSeq": "0x00",
      "dummyCfg": null,
      "protoCfg": null,
      "strDtrCfg": null
    },
    "p118": {
      "isDtr": false,
      "cmdRd": "0x7C",
      "cmdWr": "0x84",
      "modeClksCmd": 0,
      "modeClksRd": 0,
      "dummyClksCmd": 0,
      "dummyClksRd": 0,
      "enableType": "255",
      "enableSeq": "0x00",
      "dummyCfg": null,
      "protoCfg": null,
      "strDtrCfg": null
    },
    "p444s": {
      "isDtr": false,
      "cmdRd": "0xEB",
      "cmdWr": "0x02",
      "modeClksCmd": 0,
      "modeClksRd": 1,
      "dummyClksCmd": 0,
      "dummyClksRd": 9,
      "enableType": "0",
      "enableSeq": "0x14",
      "dummyCfg": {
        "isAddrReg": false,
        "cmdRegRd": "0x00",
        "cmdRegWr": "0x00",
        "cfgReg": "0x00000000",
        "shift": 0,
        "mask": "0x00",
        "bitP": 0
      },
      "protoCfg": {
        "isAddrReg": false,
        "cmdRegRd": "0x00",
        "cmdRegWr": "0x00",
        "cfgReg": "0x00000000",
        "shift": 0,
        "mask": "0x00",
        "bitP": 0
      },
      "strDtrCfg": {
        "isAddrReg": false,
        "cmdRegRd": "0x00",
        "cmdRegWr": "0x00",
        "cfgReg": "0x00000000",
        "shift": 0,
        "mask": "0x00",
        "bitP": 0
      }
    },
    "p444d": {
      "isDtr": false,
      "cmdRd": "0xEB",
      "cmdWr": "0x02",
      "modeClksCmd": 0,
      "modeClksRd": 1,
      "dummyClksCmd": 0,
      "dummyClksRd": 9,
      "enableType": "0",
      "enableSeq": "0x14",
      "dummyCfg": {
        "isAddrReg": false,
        "cmdRegRd": "0x00",
        "cmdRegWr": "0x00",
        "cfgReg": "0x00000000",
        "shift": 0,
        "mask": "0x00",
        "bitP": 0
      },
      "protoCfg": {
        "isAddrReg": false,
        "cmdRegRd": "0x00",
        "cmdRegWr": "0x00",
        "cfgReg": "0x00000000",
        "shift": 0,
        "mask": "0x00",
        "bitP": 0
      },
      "strDtrCfg": {
        "isAddrReg": false,
        "cmdRegRd": "0x00",
        "cmdRegWr": "0x00",
        "cfgReg": "0x00000000",
        "shift": 0,
        "mask": "0x00",
        "bitP": 0
      }
    },
    "p888s": null,
    "p888d": null,
    "pCustom": {
      "fxn": null
    }
  },
  "addrByteSupport": "0",
  "fourByteAddrEnSeq": "0x00",
  "cmdExtType": "NONE",
  "resetType": "0x3D",
  "deviceBusyType": "0",
  "cmdWren": "0x06",
  "cmdRdsr": "0x05",
  "srWip": 0,
  "srWel": 0,
  "cmdChipErase": "0xC7",
  "rdIdSettings": {
    "cmd": "0x9F",
    "numBytes": 5,
    "dummy4": 0,
    "dummy8": 0
  },
  "xspiWipRdCmd": "0x00",
  "xspiWipReg": "0x00000000",
  "xspiWipBit": 0,
  "flashDeviceBusyTimeout": 40000000,
  "flashPageProgTimeout": 120
}

I have problems on my QSPI configuration.
Following your example AM243x MCU+ SDK: Adding Support For a Custom Flash Device
I tried multiple times to upload the json for my QSPI, but it seems that I have problem with the automatically configure flash application.

3 months ago

0 Vaibhav Kumar 3 months ago

TI__Guru 51317 points

Hi,

I do have the flash datasheet which customer send over email.

I will review that and fill up the sysconfig values.

Once done, I will share a screenshot of it.

Thanks,

Vaibhav

0 Vaibhav Kumar 2 months ago

TI__Guru 51317 points

Hi Jan, Stefano,

I am actively reviewing this thread and will respond in sometime preferably few hours.

Thanks for your patience, as E2E was down here in TI India for a couple of days hence responses are delayed.

Thanks,

Vaibhav

0 Vaibhav Kumar 2 months ago in reply to Vaibhav Kumar

TI__Guru 51317 points

Hi Stefano,

Please try the following configurations. Please make sure to run the OSPI FLASH IO example to test this out, so you would need to make this configuration in the example.syscfg of the OSPI FLASH IO application.

OSPI Configuration as follows:

Let me know the results. If it fails while executing the application OSPI FLASH IO, I would like you to debug and tell me the exact point of failure.

Regards,

Vaibhav

0 Jan Bock 2 months ago in reply to Vaibhav Kumar

TI__Expert 3380 points

Here is a summary of my attempt to get the QSPI memory working.

Versions used:

CCS 20.3.1

SysConfig 1.21.2 (also tried with 1.25.0 but no luck)

TI Arm Clang LTS Compiler 4.0.1.00 (also tried with 4.0.4.00 but no luck)

Initially I started from the "ospi_flash_dma" example which uses HLD so in SysConfig both the FLASH and the OSPI section were configured.

To have more control I decided to switch to the "ospi_flash_dma_lld" example which uses LLD directly, so only the OSPI section is configured in SysConfig.

I tried both with and without DMA and both direct and indirect mode but led me to the same result. From the technical reference manual, I found out that the "Input Clock Frequency (Hz)" can be chosen only on a fixed set of values (which are not clear because there isn't a clock tree tool and it's hard to understand the clock chain and parameters) so I tried to change this frequency along with the "Input Clock Divider" in order to change the clock frequency fed to the QSPI IC.

The goal is to make a test which can:

Erase one or more sectors
Write data
Read back and verify the data

I tested the following protocol:

1s-1s-1s (OK <66MHz)
1s-1s-4s (FAIL I read all 0xFF, but all commands return success)
4s-4s-4s (FAIL I read all 0xFF, but all commands return success)
4s-4d-4d (FAIL I read all 0xFF, but all commands return success)

0 Vaibhav Kumar 2 months ago in reply to Jan Bock

TI__Guru 51317 points

Hi Jan,

Please ask the customer to use the configurations which I sent above to test out the OSPI FLASH IO example. If OSPI Flash IO is tested out with basic read, erase and writes working then all other applications/examples with respect to OSPI will work.

Let me know if this works for them: RE: SYSCONFIG: Sysconfig issue to upload json file for customer flash

Regards,

Vaibhav

0 Vaibhav Kumar 2 months ago in reply to Vaibhav Kumar

TI__Guru 51317 points

Hi,

Meeting Updates with ABB:

As per the call with Roberto, 1S-1S-4S is working with the configurations I have shared here: RE: SYSCONFIG: Sysconfig issue to upload json file for customer flash

Phy mode enabled also works.

Currently to inspect the working of 4S-4S-4S.

Regards,

Vaibhav

0 Vaibhav Kumar 2 months ago in reply to Vaibhav Kumar

TI__Guru 51317 points

Hi Jan,

Please ask the customer to refer to the following:

Please look at the configurations made for an already existing QSPI device. The example, which the customer can refer is going to be at the following directory:

C:\ti\mcu_plus_sdk_am243x_11_01_00_17\examples\drivers\ospi\ospi_flash_io\am243x-lp\r5fss0-0_nortos\ti-arm-clang

Regards,

Vaibhav

0 Vaibhav Kumar 18 days ago in reply to Vaibhav Kumar

TI__Guru 51317 points

Please refer the following application note: www.ti.com/.../sprads5.pdf

Arm-based microcontrollers

Arm-based microcontrollers forum

SYSCONFIG: Sysconfig issue to upload json file for customer flash