Part Number: AM2631
Other Parts Discussed in Thread: SYSCONFIG
Tool/software:
Hello,
I’m currently working with the CAN module on the AM2631, using TI’s provided low-level driver.
I’m facing an issue during testing:
When I try to send multiple CAN frames continuously (e.g., 10 frames), only the first few frames (e.g., 3) are successfully transmitted the first time.
The remaining frames are not sent immediately.
Instead, they are transmitted the next time I call the send function — together with new data, resulting in:
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Only partial frames sent during the first transmission;
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Remaining frames delayed until the next transmission;
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On the bus, I observe "remaining frames from the last call + current new data" being sent together.
The number of frames sent in the first attempt is not fixed — sometimes 3, sometimes 4 or 5, etc.
I suspect this might be related to the CAN transmit queue, mailbox configuration, or interrupt handling.
I would like to ask:
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Could you help check if the CAN configuration (mailboxes, interrupts, etc.) is correct?
Please find the CAN low-level configuration in the attached file.static void mcanInitMsgRamConfigParams(MCAN_MsgRAMConfigParams *msgRAMConfigParams) { int32_t status; MCAN_initMsgRamConfigParams(msgRAMConfigParams); /* Configure the user required msg ram params */ msgRAMConfigParams->lss = BMS_MCAN_STD_ID_FILTER_CNT; msgRAMConfigParams->lse = BMS_MCAN_EXT_ID_FILTER_CNT; msgRAMConfigParams->txBufCnt = BMS_MCAN_TX_BUFF_CNT; msgRAMConfigParams->txFIFOCnt = BMS_MCAN_TX_FIFO_CNT; /* Buffer/FIFO mode is selected */ msgRAMConfigParams->txBufMode = MCAN_TX_MEM_TYPE_BUF; msgRAMConfigParams->txEventFIFOCnt = BMS_MCAN_TX_EVENT_FIFO_CNT; msgRAMConfigParams->rxFIFO0Cnt = BMS_MCAN_FIFO_0_CNT; msgRAMConfigParams->rxFIFO1Cnt = BMS_MCAN_FIFO_1_CNT; /* FIFO blocking mode is selected */ msgRAMConfigParams->rxFIFO0OpMode = MCAN_RX_FIFO_OPERATION_MODE_BLOCKING; msgRAMConfigParams->rxFIFO1OpMode = MCAN_RX_FIFO_OPERATION_MODE_BLOCKING; status = MCAN_calcMsgRamParamsStartAddr(msgRAMConfigParams); DebugP_assert(status == CSL_PASS); return; } #define MCAN_STD_ID_FILTER_CNT (1U) /* Maximum EXT Filter Element can be configured is 64 */ #define MCAN_EXT_ID_FILTER_CNT (1U) /* Maximum TX Buffer + TX FIFO, combined can be configured is 32 */ #define MCAN_TX_BUFF_CNT (1U) #define MCAN_TX_FIFO_CNT (1U) /* Maximum TX Event FIFO can be configured is 32 */ #define MCAN_TX_EVENT_FIFO_CNT (10U) /* Maximum RX FIFO 0 can be configured is 64 */ #define MCAN_FIFO_0_CNT (32U) /* Maximum RX FIFO 1 can be configured is 64 and * rest of the memory is allocated to RX buffer which is again of max size 64 */ #define MCAN_FIFO_1_CNT (32U) #define MCAN_TX_MEM_TYPE_BUF (0U) /**< MCAN Tx Msg RAM buffers/FIFO */ #define MCAN_TX_MEM_TYPE_QUEUE (1U) /**< MCAN Tx Msg RAM Queue */ #define MCAN_DATA_SIZE_0BYTES (0U) /**< 0 byte data field */ #define MCAN_DATA_SIZE_1BYTES (1U) /**< 1 byte data field */ #define MCAN_DATA_SIZE_2BYTES (2U) /**< 2 byte data field */ #define MCAN_DATA_SIZE_3BYTES (3U) /**< 3 byte data field */ #define MCAN_DATA_SIZE_4BYTES (4U) /**< 4 byte data field */ #define MCAN_DATA_SIZE_5BYTES (5U) /**< 5 byte data field */ #define MCAN_DATA_SIZE_6BYTES (6U) /**< 6 byte data field */ #define MCAN_DATA_SIZE_7BYTES (7U) /**< 7 byte data field */ #define MCAN_DATA_SIZE_8BYTES (8U) /**< 8 byte data field */ #define MCAN_DATA_SIZE_12BYTES (9U) /**< 12 byte data field */ #define MCAN_DATA_SIZE_16BYTES (10U) /**< 16 byte data field */ #define MCAN_DATA_SIZE_20BYTES (11U) /**< 20 byte data field */ #define MCAN_DATA_SIZE_24BYTES (12U) /**< 24 byte data field */ #define MCAN_DATA_SIZE_32BYTES (13U) /**< 32 byte data field */ #define MCAN_DATA_SIZE_48BYTES (14U) /**< 48 byte data field */ #define MCAN_DATA_SIZE_64BYTES (15U) /**< 64 byte data field */
Thanks in advance for your support!
