Part Number: AM263X-MCAL-SDK
I need to have the same ADC results on Core 0 and Core 1 of R5FSS0 at the same time.
To set up the data transfer I set up EDMA on Core 0 to transfer the ADC results first to the TCMB of core 0 and then to core 1. The data transfer works fine like this. And this way, core 1 does not have the EDMA initialized.
Now my question is: is the EDMA transfer completed interrupt routed to both cores so both cores can service it at the same time? If yes, how can this be done? Can this be done with the interrupt x-bar? Or can I just enable the TPCC0 interrupt on both cores?
Thanks,
Flurin