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AM2434: Enet UDMA descriptors alignment

Vaclav Honzik
Prodigy 65 points

Part Number: AM2434
Other Parts Discussed in Thread: SYSCONFIG

Hello,

on AM243X-LP with AM243x MCU+ SDK 11.01.00 I have recently attempted to switch our networking stack on ICSS from EMAC to Switch mode.

However, in EnetUdma_initTxFreeDescQ (enet_udma_priv.c) I was getting hit by "[Enet UDMA Error] Tx DMA descriptor memory allocation failed !" assertion. I did some debugging and in EnetMem_allocDmaDesc the dequeued dma descriptor fails the ENET_UTILS_IS_ALIGNED macro and therefore the function returns it back to the queue and returns null. This null is the reason for the assertion mentioned above.

The alignment to check passed from EnetUdma_initTxFreeDescQ is UDMA_CACHELINE_ALIGNMENT (=128). However the gDmaDescMemInfoArray, which to my limited understanding is the underlying memory for (or is at least related to) dmaDescFreeQ, in the SysCfg generated ti_enet_config.c has alignment ENETDMA_CACHELINE_ALIGNMENT (=32).

When I have excluded the "ti_enet_config.c" from SysCfg build and changed the alignment of the gDmaDescMemArray and gDmaDescMemInfoArray from ENETDMA_CACHELINE_ALIGNMENT to UDMA_CACHELINE_ALIGNMENT our application started working again.

I won't pretend I understand all of this to be honest, these are just my observations :) I have attached the Switch mode syscfg file (note the excluded enet_config file). Just to be clear, I have it working now using the above change but I thought I should report this.

Cheers,
Vaclav
  • 0
    Prodigy 65 points

    Fullscreen 0753.example.syscfg.txt Download 
    /**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM243x_ALX_beta" --part "ALX" --package "ALX" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM243x@11.00.00"
 * @v2CliArgs --device "AM2434" --package "FCCSP (ALX)" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM243x@11.00.00"
 * @versions {"tool":"1.22.0+3893"}
 */
scripting.excludeFromBuild("ti_enet_config.c");

/**
 * Import the modules used in this configuration.
 */
const eeprom          = scripting.addModule("/board/eeprom/eeprom", {}, false);
const eeprom1         = eeprom.addInstance();
const flash           = scripting.addModule("/board/flash/flash", {}, false);
const flash1          = flash.addInstance();
const gp_timer        = scripting.addModule("/drivers/gp_timer/gp_timer", {}, false);
const gp_timer1       = gp_timer.addInstance();
const gpio            = scripting.addModule("/drivers/gpio/gpio", {}, false);
const gpio1           = gpio.addInstance();
const gpio2           = gpio.addInstance();
const gpio3           = gpio.addInstance();
const gpio4           = gpio.addInstance();
const gpio5           = gpio.addInstance();
const i2c             = scripting.addModule("/drivers/i2c/i2c", {}, false);
const i2c1            = i2c.addInstance();
const ipc             = scripting.addModule("/drivers/ipc/ipc");
const mcspi           = scripting.addModule("/drivers/mcspi/mcspi", {}, false);
const mcspi1          = mcspi.addInstance();
const pruicss         = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
const pruicss1        = pruicss.addInstance();
const clock           = scripting.addModule("/kernel/dpl/clock");
const debug_log       = scripting.addModule("/kernel/dpl/debug_log");
const dpl_cfg         = scripting.addModule("/kernel/dpl/dpl_cfg");
const mpu_armv7       = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71      = mpu_armv7.addInstance();
const mpu_armv72      = mpu_armv7.addInstance();
const mpu_armv73      = mpu_armv7.addInstance();
const mpu_armv74      = mpu_armv7.addInstance();
const mpu_armv75      = mpu_armv7.addInstance();
const default_linker  = scripting.addModule("/memory_configurator/default_linker", {}, false);
const default_linker1 = default_linker.addInstance();
const general         = scripting.addModule("/memory_configurator/general", {}, false);
const general1        = general.addInstance();
const region          = scripting.addModule("/memory_configurator/region", {}, false);
const region1         = region.addInstance();
const section         = scripting.addModule("/memory_configurator/section", {}, false);
const section1        = section.addInstance();
const section2        = section.addInstance();
const section3        = section.addInstance();
const section4        = section.addInstance();
const section5        = section.addInstance();
const section6        = section.addInstance();
const section7        = section.addInstance();
const section8        = section.addInstance();
const section9        = section.addInstance();
const section10       = section.addInstance();
const section11       = section.addInstance();
const enet_icss       = scripting.addModule("/networking/enet_icss/enet_icss", {}, false);
const enet_icss1      = enet_icss.addInstance();

/**
 * Write custom configuration values to the imported modules.
 */
eeprom1.$name = "CONFIG_EEPROM0";

flash1.$name                        = "CONFIG_FLASH0";
flash1.peripheralDriver.$name       = "CONFIG_OSPI0";
flash1.peripheralDriver.child.$name = "drivers_ospi_v0_ospi_v0_template0";

gp_timer1.$name                   = "GPTIMER_IPC_CHECK";
gp_timer1.enableIntr              = true;
gp_timer1.timerConfigMode         = "OUTPUT_COMPARE";
gp_timer1.advancedConfig          = true;
gp_timer1.cntCompareValComp       = 0x9C3;
gp_timer1.compareMatchCallbackFxn = "GpTimerIpcCallback";
gp_timer1.TIMER.$assign           = "DMTIMER6";

gpio1.$name          = "GPIO_LD1";
gpio1.pinDir         = "OUTPUT";
gpio1.rx             = true;
gpio1.defaultValue   = "1";
gpio1.GPIO_n.$assign = "GPMC0_AD7";

gpio2.$name          = "GPIO_LD2";
gpio2.pinDir         = "OUTPUT";
gpio2.rx             = true;
gpio2.GPIO_n.$assign = "UART0_RTSn";

gpio3.$name          = "GPIO_LD3";
gpio3.pinDir         = "OUTPUT";
gpio3.rx             = true;
gpio3.GPIO_n.$assign = "PRG0_PRU1_GPO18";

gpio4.$name          = "GPIO_LD4";
gpio4.pinDir         = "OUTPUT";
gpio4.defaultValue   = "1";
gpio4.rx             = true;
gpio4.GPIO_n.$assign = "PRG0_PRU1_GPO19";

gpio5.pinDir         = "OUTPUT";
gpio5.defaultValue   = "1";
gpio5.$name          = "GPIO_SPI_CNV";
gpio5.rx             = true;
gpio5.pu_pd          = "pu";
gpio5.GPIO_n.$assign = "SPI0_CS1";

i2c1.$name               = "CONFIG_I2C0";
eeprom1.peripheralDriver = i2c1;
i2c1.I2C.$assign         = "I2C0";
i2c1.I2C_child.$name     = "drivers_i2c_v0_i2c_v0_template0";

ipc.r5fss1_0 = "notify";
ipc.r5fss1_1 = "notify";
ipc.m4fss0_0 = "notify";
ipc.r5fss0_1 = "notify";

mcspi1.$name                   = "CONFIG_MCSPI0";
mcspi1.pinMode                 = 3;
mcspi1.mcspiChannel[0].$name   = "CONFIG_MCSPI_CH0";
mcspi1.mcspiChannel[0].bitRate = 3333333;
mcspi1.child.$name             = "drivers_mcspi_v0_mcspi_v0_template0";

debug_log.enableUartLog            = true;
debug_log.enableSharedMemLog       = true;
debug_log.enableSharedMemLogReader = true;
debug_log.enableLogZoneInfo        = true;
debug_log.uartLog.$name            = "CONFIG_UART0";
debug_log.uartLog.UART.$assign     = "USART0";

const uart_v0_template  = scripting.addModule("/drivers/uart/v0/uart_v0_template", {}, false);
const uart_v0_template1 = uart_v0_template.addInstance({}, false);
uart_v0_template1.$name = "drivers_uart_v0_uart_v0_template0";
debug_log.uartLog.child = uart_v0_template1;

mpu_armv71.$name             = "CONFIG_MPU_REGION0";
mpu_armv71.size              = 31;
mpu_armv71.attributes        = "Device";
mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv71.allowExecute      = false;

mpu_armv72.$name             = "CONFIG_MPU_REGION1";
mpu_armv72.size              = 15;
mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv73.$name             = "CONFIG_MPU_REGION2";
mpu_armv73.baseAddr          = 0x41010000;
mpu_armv73.size              = 15;
mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv74.$name             = "CONFIG_MPU_REGION3";
mpu_armv74.baseAddr          = 0x70000000;
mpu_armv74.size              = 21;
mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv75.$name        = "CONFIG_MPU_REGION4";
mpu_armv75.baseAddr     = 0x701D0000;
mpu_armv75.size         = 16;
mpu_armv75.attributes   = "NonCached";
mpu_armv75.allowExecute = false;

default_linker1.$name = "memory_configurator_default_linker0";

general1.$name        = "CONFIG_GENERAL0";
general1.stack_size   = 8192;
general1.linker.$name = "TIARMCLANG0";

region1.$name                               = "MEMORY_REGION_CONFIGURATION0";
region1.memory_region.create(9);
region1.memory_region[0].type               = "TCMA_R5F";
region1.memory_region[0].$name              = "R5F_VECS";
region1.memory_region[0].size               = 0x40;
region1.memory_region[0].auto               = false;
region1.memory_region[1].type               = "TCMA_R5F";
region1.memory_region[1].$name              = "R5F_TCMA";
region1.memory_region[1].size               = 0x7FC0;
region1.memory_region[2].type               = "TCMB_R5F";
region1.memory_region[2].$name              = "R5F_TCMB0";
region1.memory_region[2].size               = 0x8000;
region1.memory_region[3].$name              = "NON_CACHE_MEM";
region1.memory_region[3].auto               = false;
region1.memory_region[3].manualStartAddress = 0x70060000;
region1.memory_region[3].size               = 0x8000;
region1.memory_region[4].$name              = "MSRAM";
region1.memory_region[4].auto               = false;
region1.memory_region[4].manualStartAddress = 0x70080000;
region1.memory_region[4].size               = 0x150000;
region1.memory_region[5].type               = "FLASH";
region1.memory_region[5].$name              = "FLASH";
region1.memory_region[5].auto               = false;
region1.memory_region[5].manualStartAddress = 0x60100000;
region1.memory_region[5].size               = 0x80000;
region1.memory_region[6].$name              = "USER_SHM_MEM";
region1.memory_region[6].auto               = false;
region1.memory_region[6].manualStartAddress = 0x701D0000;
region1.memory_region[6].size               = 0x180;
region1.memory_region[6].isShared           = true;
region1.memory_region[6].shared_cores       = ["m4fss0-0"];
region1.memory_region[7].auto               = false;
region1.memory_region[7].manualStartAddress = 0x701D0180;
region1.memory_region[7].size               = 0x3E80;
region1.memory_region[7].$name              = "LOG_SHM_MEM";
region1.memory_region[7].isShared           = true;
region1.memory_region[7].shared_cores       = ["m4fss0-0"];
region1.memory_region[8].auto               = false;
region1.memory_region[8].manualStartAddress = 0x701D4000;
region1.memory_region[8].size               = 0xC000;
region1.memory_region[8].$name              = "RTOS_NORTOS_IPC_SHM_MEM";
region1.memory_region[8].isShared           = true;
region1.memory_region[8].shared_cores       = ["m4fss0-0"];

section1.$name                        = "Vector Table";
section1.load_memory                  = "R5F_VECS";
section1.group                        = false;
section1.output_section.create(1);
section1.output_section[0].$name      = ".vectors";
section1.output_section[0].palignment = true;

section2.$name                        = "Text Segments";
section2.load_memory                  = "MSRAM";
section2.output_section.create(5);
section2.output_section[0].$name      = ".text.hwi";
section2.output_section[0].palignment = true;
section2.output_section[1].$name      = ".text.cache";
section2.output_section[1].palignment = true;
section2.output_section[2].$name      = ".text.mpu";
section2.output_section[2].palignment = true;
section2.output_section[3].$name      = ".text.boot";
section2.output_section[3].palignment = true;
section2.output_section[4].$name      = ".text:abort";
section2.output_section[4].palignment = true;

section3.$name                        = "Code and Read-Only Data";
section3.load_memory                  = "MSRAM";
section3.output_section.create(2);
section3.output_section[0].$name      = ".text";
section3.output_section[0].palignment = true;
section3.output_section[1].$name      = ".rodata";
section3.output_section[1].palignment = true;

section4.$name                        = "Data Segment";
section4.load_memory                  = "MSRAM";
section4.output_section.create(1);
section4.output_section[0].$name      = ".data";
section4.output_section[0].palignment = true;

section5.$name                                   = "Memory Segments";
section5.load_memory                             = "MSRAM";
section5.output_section.create(3);
section5.output_section[0].$name                 = ".bss";
section5.output_section[0].palignment            = true;
section5.output_section[0].output_sections_start = "__BSS_START";
section5.output_section[0].output_sections_end   = "__BSS_END";
section5.output_section[1].$name                 = ".sysmem";
section5.output_section[1].palignment            = true;
section5.output_section[2].$name                 = ".stack";
section5.output_section[2].palignment            = true;

section6.$name                                    = "Stack Segments";
section6.load_memory                              = "MSRAM";
section6.output_section.create(5);
section6.output_section[0].$name                  = ".irqstack";
section6.output_section[0].output_sections_start  = "__IRQ_STACK_START";
section6.output_section[0].output_sections_end    = "__IRQ_STACK_END";
section6.output_section[0].input_section.create(1);
section6.output_section[0].input_section[0].$name = ". = . + __IRQ_STACK_SIZE;";
section6.output_section[1].$name                  = ".fiqstack";
section6.output_section[1].output_sections_start  = "__FIQ_STACK_START";
section6.output_section[1].output_sections_end    = "__FIQ_STACK_END";
section6.output_section[1].input_section.create(1);
section6.output_section[1].input_section[0].$name = ". = . + __FIQ_STACK_SIZE;";
section6.output_section[2].$name                  = ".svcstack";
section6.output_section[2].output_sections_start  = "__SVC_STACK_START";
section6.output_section[2].output_sections_end    = "__SVC_STACK_END";
section6.output_section[2].input_section.create(1);
section6.output_section[2].input_section[0].$name = ". = . + __SVC_STACK_SIZE;";
section6.output_section[3].$name                  = ".abortstack";
section6.output_section[3].output_sections_start  = "__ABORT_STACK_START";
section6.output_section[3].output_sections_end    = "__ABORT_STACK_END";
section6.output_section[3].input_section.create(1);
section6.output_section[3].input_section[0].$name = ". = . + __ABORT_STACK_SIZE;";
section6.output_section[4].$name                  = ".undefinedstack";
section6.output_section[4].output_sections_start  = "__UNDEFINED_STACK_START";
section6.output_section[4].output_sections_end    = "__UNDEFINED_STACK_END";
section6.output_section[4].input_section.create(1);
section6.output_section[4].input_section[0].$name = ". = . + __UNDEFINED_STACK_SIZE;";

section7.$name                        = "Initialization and Exception Handling";
section7.load_memory                  = "MSRAM";
section7.output_section.create(3);
section7.output_section[0].$name      = ".ARM.exidx";
section7.output_section[0].palignment = true;
section7.output_section[1].$name      = ".init_array";
section7.output_section[1].palignment = true;
section7.output_section[2].$name      = ".fini_array";
section7.output_section[2].palignment = true;

section8.$name                       = "User Shared Memory";
section8.type                        = "NOLOAD";
section8.load_memory                 = "USER_SHM_MEM";
section8.group                       = false;
section8.output_section.create(1);
section8.output_section[0].$name     = ".bss.user_shared_mem";
section8.output_section[0].alignment = 0;

section9.$name                       = "Log Shared Memory";
section9.load_memory                 = "LOG_SHM_MEM";
section9.type                        = "NOLOAD";
section9.group                       = false;
section9.output_section.create(1);
section9.output_section[0].$name     = ".bss.log_shared_mem";
section9.output_section[0].alignment = 0;

section10.$name                       = "IPC Shared Memory";
section10.type                        = "NOLOAD";
section10.load_memory                 = "RTOS_NORTOS_IPC_SHM_MEM";
section10.group                       = false;
section10.output_section.create(1);
section10.output_section[0].$name     = ".bss.ipc_vring_mem";
section10.output_section[0].alignment = 0;

section11.$name                       = "Non Cacheable Memory";
section11.load_memory                 = "NON_CACHE_MEM";
section11.group                       = false;
section11.type                        = "NOLOAD";
section11.output_section.create(1);
section11.output_section[0].$name     = ".bss.nocache";
section11.output_section[0].alignment = 0;

enet_icss1.$name                        = "CONFIG_ENET_ICSS0";
enet_icss1.mdioMode                     = "MDIO_MODE_MANUAL";
enet_icss1.PktInfoOnlyEnable            = true;
enet_icss1.phyToMacInterfaceMode        = "RGMII";
enet_icss1.QoS                          = 3;
enet_icss1.LargePoolPktCount            = 32;
enet_icss1.txDmaChannel[0].$name        = "ENET_DMA_TX_CH0";
enet_icss1.rxDmaChannel[0].$name        = "ENET_DMA_RX_CH0";
enet_icss1.rxDmaChannel[0].PacketsCount = 16;
enet_icss1.rxDmaChannel[1].$name        = "ENET_DMA_RX_CH1";
enet_icss1.rxDmaChannel[1].chIdx        = 1;
enet_icss1.rxDmaChannel[1].macAddrCount = 0;
enet_icss1.rxDmaChannel[1].PacketsCount = 16;
enet_icss1.netifInstance.create(1);
enet_icss1.netifInstance[0].$name       = "NETIF_INST_ID0";
enet_icss1.netifInstance[0].rxDmaChNum  = ["0","1"];
enet_icss1.PRU_ICSSG1_RGMII1.$assign    = "PRU_ICSSG1_RGMII1";

const ethphy_cpsw_icssg  = scripting.addModule("/board/ethphy_cpsw_icssg/ethphy_cpsw_icssg", {}, false);
const ethphy_cpsw_icssg1 = ethphy_cpsw_icssg.addInstance({}, false);
ethphy_cpsw_icssg1.$name = "CONFIG_ENET_ETHPHY0";
enet_icss1.ethphy2       = ethphy_cpsw_icssg1;

const ethphy_cpsw_icssg2 = ethphy_cpsw_icssg.addInstance({}, false);
ethphy_cpsw_icssg2.$name = "CONFIG_ENET_ETHPHY1";
enet_icss1.ethphy3       = ethphy_cpsw_icssg2;

enet_icss1.icss                          = pruicss1;
pruicss1.$name                           = "CONFIG_PRU_ICSS1";
pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
pruicss1.intcMapping.create(2);
pruicss1.intcMapping[0].$name            = "CONFIG_ICSS1_INTC_MAPPING0";
pruicss1.intcMapping[0].event            = "41";
pruicss1.intcMapping[0].channel          = "7";
pruicss1.intcMapping[0].host             = "8";
pruicss1.intcMapping[1].$name            = "CONFIG_ICSS1_INTC_MAPPING1";
pruicss1.intcMapping[1].event            = "53";
pruicss1.intcMapping[1].channel          = "7";
pruicss1.intcMapping[1].host             = "8";

const udma         = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1        = udma.addInstance({}, false);
mcspi1.udmaDriver  = udma1;
enet_icss1.udmaDrv = udma1;

/**
 * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
 * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
 * re-solve from scratch.
 */
flash1.peripheralDriver.OSPI.$suggestSolution            = "OSPI0";
flash1.peripheralDriver.OSPI.CLK.$suggestSolution        = "OSPI0_CLK";
flash1.peripheralDriver.OSPI.CSn0.$suggestSolution       = "OSPI0_CSn0";
flash1.peripheralDriver.OSPI.D3.$suggestSolution         = "OSPI0_D3";
flash1.peripheralDriver.OSPI.D2.$suggestSolution         = "OSPI0_D2";
flash1.peripheralDriver.OSPI.D1.$suggestSolution         = "OSPI0_D1";
flash1.peripheralDriver.OSPI.D0.$suggestSolution         = "OSPI0_D0";
i2c1.I2C.SCL.$suggestSolution                            = "I2C0_SCL";
i2c1.I2C.SDA.$suggestSolution                            = "I2C0_SDA";
mcspi1.SPI.$suggestSolution                              = "SPI0";
mcspi1.SPI.CLK.$suggestSolution                          = "SPI0_CLK";
mcspi1.SPI.D0.$suggestSolution                           = "SPI0_D0";
mcspi1.SPI.D1.$suggestSolution                           = "SPI0_D1";
debug_log.uartLog.UART.RXD.$suggestSolution              = "UART0_RXD";
debug_log.uartLog.UART.TXD.$suggestSolution              = "UART0_TXD";
enet_icss1.PRU_ICSSG1_MDIO.$suggestSolution              = "PRU_ICSSG1_MDIO0";
enet_icss1.PRU_ICSSG1_MDIO.MDC.$suggestSolution          = "PRG1_MDIO0_MDC";
enet_icss1.PRU_ICSSG1_MDIO.MDIO.$suggestSolution         = "PRG1_MDIO0_MDIO";
enet_icss1.PRU_ICSSG1_IEP.$suggestSolution               = "PRU_ICSSG1_IEP0";
enet_icss1.PRU_ICSSG1_IEP.EDC_LATCH_IN0.$suggestSolution = "PRG1_PRU0_GPO18";
enet_icss1.PRU_ICSSG1_IEP.EDC_SYNC_OUT0.$suggestSolution = "PRG1_PRU0_GPO19";
enet_icss1.PRU_ICSSG1_RGMII1.RD0.$suggestSolution        = "PRG1_PRU0_GPO0";
enet_icss1.PRU_ICSSG1_RGMII1.RD1.$suggestSolution        = "PRG1_PRU0_GPO1";
enet_icss1.PRU_ICSSG1_RGMII1.RD2.$suggestSolution        = "PRG1_PRU0_GPO2";
enet_icss1.PRU_ICSSG1_RGMII1.RD3.$suggestSolution        = "PRG1_PRU0_GPO3";
enet_icss1.PRU_ICSSG1_RGMII1.RXC.$suggestSolution        = "PRG1_PRU0_GPO6";
enet_icss1.PRU_ICSSG1_RGMII1.RX_CTL.$suggestSolution     = "PRG1_PRU0_GPO4";
enet_icss1.PRU_ICSSG1_RGMII1.TD0.$suggestSolution        = "PRG1_PRU0_GPO11";
enet_icss1.PRU_ICSSG1_RGMII1.TD1.$suggestSolution        = "PRG1_PRU0_GPO12";
enet_icss1.PRU_ICSSG1_RGMII1.TD2.$suggestSolution        = "PRG1_PRU0_GPO13";
enet_icss1.PRU_ICSSG1_RGMII1.TD3.$suggestSolution        = "PRG1_PRU0_GPO14";
enet_icss1.PRU_ICSSG1_RGMII1.TXC.$suggestSolution        = "PRG1_PRU0_GPO16";
enet_icss1.PRU_ICSSG1_RGMII1.TX_CTL.$suggestSolution     = "PRG1_PRU0_GPO15";
enet_icss1.PRU_ICSSG1_RGMII2.$suggestSolution            = "PRU_ICSSG1_RGMII2";
enet_icss1.PRU_ICSSG1_RGMII2.RD0.$suggestSolution        = "PRG1_PRU1_GPO0";
enet_icss1.PRU_ICSSG1_RGMII2.RD1.$suggestSolution        = "PRG1_PRU1_GPO1";
enet_icss1.PRU_ICSSG1_RGMII2.RD2.$suggestSolution        = "PRG1_PRU1_GPO2";
enet_icss1.PRU_ICSSG1_RGMII2.RD3.$suggestSolution        = "PRG1_PRU1_GPO3";
enet_icss1.PRU_ICSSG1_RGMII2.RXC.$suggestSolution        = "PRG1_PRU1_GPO6";
enet_icss1.PRU_ICSSG1_RGMII2.RX_CTL.$suggestSolution     = "PRG1_PRU1_GPO4";
enet_icss1.PRU_ICSSG1_RGMII2.TD0.$suggestSolution        = "PRG1_PRU1_GPO11";
enet_icss1.PRU_ICSSG1_RGMII2.TD1.$suggestSolution        = "PRG1_PRU1_GPO12";
enet_icss1.PRU_ICSSG1_RGMII2.TD2.$suggestSolution        = "PRG1_PRU1_GPO13";
enet_icss1.PRU_ICSSG1_RGMII2.TD3.$suggestSolution        = "PRG1_PRU1_GPO14";
enet_icss1.PRU_ICSSG1_RGMII2.TXC.$suggestSolution        = "PRG1_PRU1_GPO16";
enet_icss1.PRU_ICSSG1_RGMII2.TX_CTL.$suggestSolution     = "PRG1_PRU1_GPO15";

  • 0 in reply to Vaclav Honzik
    TI__Genius 9520 points

    Hi,

    The DMA descriptors are 128 aligned in both the ti_enet_config.c and while allocating the desc queues in enet_udma_priv.c using EnetMem_allocDmaDesc. This did you make any changes in the template files? The alignment of gDmaDescMemInfoArray should be UDMA_CACHELINE_ALIGNMENT. 

    Can you please share more details on which example that you are trying to use? Any additional details that you can share will be helpful to analyse the situation.

    Regards,
    Teja.

  • 0 in reply to Teja Rowthu
    Prodigy 65 points

    Heya Teja,

    I am not aware of any changes to template files in our SDK. I searched for the gDmaDescMemInfoArray symbol in our 11.00.00 SDK copy and found it in two templates:
    1) source\networking\enet\core\sysconfig\networking\.meta\enet_cpsw\templates\enet_app_memutils_cfg_udma.c.xdt
    This one has UDMA_CACHELINE_ALIGNMENT

    2) source\networking\enet\core\sysconfig\networking\.meta\enet_icss\templates\enet_app_memutils_cfg.c.xdt
    This one has ENETDMA_CACHELINE_ALIGNMENT

    We are using ICSS so this seems promising to me as the possible cause? We have moved past examples at this point, and I don't necessarily have time to try to reproduce this with an example, but I will be happy to provide more context. I do believe Syscfg is just generating wrong alignment in this case.

    Cheers,
    Vaclav

  • 0 in reply to Vaclav Honzik
    TI__Genius 9520 points

    Hi Vaclav,

    Ideally, the alignment should be with UDMA_CACHELINE_ALIGNMENT. I will check internally if there were any reasons for making it ENETDMA_CACHELINE_ALIGNMENT, which is now leading to issues. Please expect a response in 2 days for confirmation and preferred way of going forward. 

    Thanks and regards,
    Teja.

  • 0 in reply to Teja Rowthu
    Prodigy 65 points

    Great, thank you for your help. Knowing that UDMA_ is desired is good enough for us.