TMS570LS3134: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1412515/tms570ls3134-

Hi Samet,

The TMS570LS3137, as part of the Hercules safety MCU family, implements both LBIST (Logic Built-In Self-Test) and PBIST (Programmable Built-In Self-Test) as hardware-based safety mechanisms. From the available information, these self-test mechanisms appear to be primarily hardware-based implementations rather than microcode-based solutions. The PBIST is specifically described as a "programmable test engine" that applies different memory test algorithms to internal SRAM and Flash on the device.

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Thanks & regards,
Jagadish.

Hi Jagadish,

Thank you for your reply. In our previous conversation, you said "ROM to hold the PBIST related algorithms in the controller" as follows. I understand that there is code here.

1) I understand there is code because the algorithm is stored in the ROM. But you're currently saying it's "hardware-based safety mechanisms." Can you provide information for this?

2) Regardless of whether the safety mechanisms are software-based or hardware-based, how did TI verify the safety algorithms?"

Hi Samet,

Apologies for the delayed response, due to other priority issues, i didn't get time for this issue.

Samet Varan said:

1) I understand there is code because the algorithm is stored in the ROM. But you're currently saying it's "hardware-based safety mechanisms." Can you provide information for this?

Only algorithms and test patterns will be stored in ROM memory, 

PBIST is a hardware-based safety mechanism, even though algorithms are stored in ROM. Here's why:

The PBIST architecture consists of:

• A dedicated hardware coprocessor with a specialized instruction set specifically designed for memory testing
• Dedicated hardware controller with specialized pipeline and register set.

Samet Varan said:

2) Regardless of whether the safety mechanisms are software-based or hardware-based, how did TI verify the safety algorithms?"

1. TÜV SÜD Certified Development Process:

• TI has TÜV SÜD certification for their Functional Safety Hardware and Software Development Process
• The development process ensures systematic capability of ASIL-D (ISO 26262) and SIL-3 (IEC 61508)

2. Independent Safety Assessment:

• FMEDA (Failure Mode, Effects and Diagnostic Analysis) - provides detailed analysis of failure modes and diagnostic coverage of safety mechanisms
• Technical Reports on Random Hardware Capability - independently assessed
• Technical Reports on Systematic Capability - independently assessed
• Safety Analysis Reports (SAR) - contains results according to functional safety standards

3. Algorithm Validation:

• PBIST uses March-13n algorithm for SRAMs, which provides "very high diagnostic coverage" at the transistor level
• For ROMs, uses triple_read_xor_read algorithm
• Over 300 safety mechanisms defined and independently assessed by TÜV SÜD for effectiveness

4. Verification Methods:

• Hardware component verification and validation (V&V) executed to support internal development
• Fault injection testing capabilities to validate diagnostic coverage
• Compliance with ISO 26262 hardware and software development processes

5. Diagnostic Coverage Validation:

• PBIST provides >90% permanent fault coverage for Hardware BIST
• Diagnostic coverage values are documented in the FMEDA and independently assessed
• The March-13n algorithm specifically targets transistor-level faults in memory

The Hercules SafeTI Diagnostic Library is a collection of software functions and response handlers for various safety features of the Hercules Safety MCUs.

SAFETI_DIAG_LIB Driver or library | TI.com

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Thanks & regards,
Jagadish.

Hi Jagadish,

Thank you for your reply.

In reference to the TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller (SPNU499C, March 2018, Rev C), specifically Chapter 7 - Programmable Built-In Self-Test (PBIST) Module, Section 7.3.1, titled "PBIST Sequence," item 9 mentions: "Write a value of 3h to the ROM mask register should the microcode for the Algorithms as well as the RAM groups be loaded from the on-chip PBIST ROM." Based on this statement, I understand that the PBIST module includes microcode.

According to AMC 20-152A, Section 6.4.1.2, titled "Considerations when the COTS Device has Embedded Microcode," COTS devices containing microcode must be controlled by a configuration management system and qualified together with the device by the device manufacturer.

1. Could you kindly confirm whether the TMS570LS3134 products have been controlled via the configuration management system and qualified together with the device by the device manufacturer?
2. Also the TI development process has been certified by TÜV SÜD, as mentioned in your previous response. Are the microcode verification activities being conducted as part of this certification process?
3. You mentioned that the algorithm was independently assessedby TÜV SÜD and referred to the hardware verification methods. What verification activities were carried out for the microcode during these activities?

Thanks & regards,

Hi Samet,

I didn't involve in the TUV SUD certification process of these devices.

My senior colleague QJ Wang  might have knowledge on this. I am looping him for assistance.

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Thanks & regards,
Jagdish.

Hi QJ Wang,

Could you please share any documentation or certification you may have regarding the microcode, other than the certificate Z10 088989 0017 Rev. 00?
If a Non-Disclosure Agreement (NDA) is required, we can arrange one.

Thanks & regards