Part Number: MSPM0G1507
Hello,
I had a customer reach out wanting to know a little more on the formatting of the SRAM parity bits in the parity memory region.
When they write to the SRAM parity protected region they expect to see the parity bits updated at the corresponding address + offset in the SRAM_PARITY_Data section. So for example a 32 bit write to 0x20100000 would yield a corresponding parity value at 0x20300000.
However what we're seeing is that multiple addresses get updated on a 32 bit write in the sram parity data section.
I took the sram_parity example and modified it slightly and stepped through the code to observe the memory regions as the data got written:
After the first write:
So what we see is that at 0x20300040 the parity bit gets written in the lower nibble, but then also gets mirrored at 0x20300044.
Then the next 32 bit write seems to write its parity bits at 0x20300044's upper nibble and again at 0x20300048:
And so on for the other two words:
To check and see if the behavior truly is to mirror the parity bits, I also checked changed one of the values in SRAM in the memory browser and saw that changing 1 bit in a 32 bit word changed both sets of parity bits.
Is this expected behavior? How come the TRM doesn't mention that the parity module updates the SRAM parity in this way?
Munan
