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MSPM0G1519: Changing CLK2X_DIV on the Fly

Philip Neaves
Intellectual 340 points

Part Number: MSPM0G1519

Hello.

I am generating GPIO data patterns via DMA and a LUT; all works good.

I want to change how long the LUT takes to be output to the GPIO to reduce LUT size (not use padding).

I have been changing CLK2X_DIV on the fly and it seems to work; this may not be "safe"....do I need to disable the PLL ? 

Since the divider is at the output of the PLL (and not in a feedback loop) then one would hope the CLK2X_DIV update is synchronised accordingly to avoid any runt pulses....????

Can't find anything in the TRM about it.

Code is:

gSYSPLLConfig.rDivClk2x=0x0f; //div 16 (20 MHz)
DL_SYSCTL_configSYSPLL( &gSYSPLLConfig);
 
DO DMA
 
gSYSPLLConfig.rDivClk2x=0x03; // div 4 (80 MHz)
DL_SYSCTL_configSYSPLL( &gSYSPLLConfig);
 
--
Thanks
 

 

 

 

  • 0
    TI__Mastermind 27050 points

    Hi Philip,

    Is there anything else in your system that is going to be impacted by this change in the MCLK frequency? Timers, communication peripherals etc.

    The driverlib function DL_SYSCTL_configSYSPLL( &gSYSPLLConfig); will disable the syspll, adjust all settings, then reenable the syspll and wait. If your pseudo code accurate, I don't foresee any issues.