Hi Team,
Posting on behalf of our customer.
I'm using a TMS570LC4357 Rev B chip configured as a master using CS4_N with a 32-bit EMIF asynchronous interface and WAIT enabled, connected to an external device. However, when testing 32-bit read accesses in C-code, I observed that at offset 0x8, there is only one half-cycle (looks as 16-bit) access, meaning the chip select goes active only once. In contrast, read accesses at offsets 0x0, 0x4 and upwards appear correct (except the 0x8) giving correct data, showing two chip select activations corresponding to a full 32-bit access (2 × 16-bit transfers). If I perform the read at offset 0x8 twice, the second read behaves correctly, the chip select toggles twice, and the correct 32-bit value is returned at the second read, the first read gives always 0x0 as result for offset 0x8.
-What is the explanation of this behaviour and what registers are possible to read out to clarify the problem?
Regards,
Danilo
