Part Number: AM263P4-Q1
Other Parts Discussed in Thread: AM2632
Hi,
I am observing inconsistent ESM flag behavior during ECC error injection testing on the AM2632 controller. Below are the detailed test scenarios and observations:
Scenario 1: ATCM Core 0 Memory
- Inject a 1-bit error and clear it.
- Then inject a 2-bit error and observe the ESM status registers.
Observation:
When the 1-bit error is injected first followed by the 2-bit error, the ESM status flags are not set for the 2-bit error.
However, in the SDK reference example, the order is reversed (2-bit error injected first, then 1-bit error), and in that sequence, the ESM flags are set correctly.
Query:
Why does the ESM fail to set status flags when the 1-bit error is injected before the 2-bit error?
Scenario 2: ICSSM Memory
- Inject a 1-bit error for RAM ID 1 and clear it.
- Then inject a 1-bit error again for RAM ID 2 and check the ESM register flags.
Observation:
When injecting 1-bit errors sequentially for different RAM IDs within the same ICSSM memory, the ESM flags are set only for the first RAM ID, while the subsequent RAM IDs do not trigger ESM flag updates.
Query:
Why are the ESM flags not set for subsequent RAM IDs when injecting 1-bit errors sequentially within the same memory instance?
