AM2431: Share same CPSW Core with different M4 and R5F cores

Hi Prassana,

Prasanna Raghunathan said:

Can the M4 run the SBL with keeping R5 in reset ? or SBL can only be run by R5F ?

Running SBL from M4 is not possible, SBL can only execute in R5F.

I am routing this thread to another expert to help you with the other 2 queries, please wait for their response.

Best Regards,

Meet.

Hello Prassana,

We can't use the OSPI interface from the M4F core.

It is technically possible to share the OSPI Flash and CPSW peripheral between different cores, but only at different times.

Before switching ownership between cores, the active core must deinitialize the peripheral.

Later, you can initiate a Warm reset between ownership changes — that’s actually the cleanest way to ensure all IPs return to a known reset state.

The OPSI and CPSW will use the DMA channels. So, we need to reset the SOC to assign the DMA channels to different cores.

After the reset, the next core can reconfigure and reinitialize the OSPI or CPSW modules safely.

And one more thing is that when you are trying to use the CPSW in multiple cores, we need to allocate CPSW DMA channels in multiple cores as well.

Regards,

Anil.

Hello Prassana,

If you share your requirements fully , we can try to help you in better way .

Regards,

Anil.

Hi Anil,

Thanks for the detailed response. Yes, I have noticed the DMA channel issue when I tried to re-init the CPSW core when using LWIP from the same R5F core after an initial failure and found that the resource cannot be allocated for a second time. This is precisely why I wanted to know a clean way to do the handoff.

Here is my use-case and thought-process:

I am using the AM2431 variant. I have a work-around with my own Ethernet-App which mimics Ethernet Bootup mode. The SBL checks the meta-data/cookie on the flash and loads the Ethernet-App which does the FW image application update to flash via ethernet, updates the meta-data/cookie on flash and resets the board. Now the FW image application will be loaded by SBL upon checking the meta-data/cookie and run by R5F.

I am severely constrained by the internal memory and I wanted to see if I can utilize the M4 to run the Ethernet-App and perform the FW update. This gives me access to the extra 256KB RAM on M4 + the 2MB OCSRAM. This way the functionality is segmented between cores and I get to use the 256KB RAM on M4. I need to be able to share both the OSPI and CPSW peripherals between the cores. 

I found this thread that talks about making Ethernet Boot on AM243x. I am yet to test this one out. Can you please clarify ?

(1) AM2431: Support of Ethernet Primary Boot & Backup Boot - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

Thanks,

Prasanna

Hello Prasanna,

I am routing your query to Ethernet Experts  .

Regards,

Anil.