• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 32 subscribers
  • Views 219 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

AM263P4: CAN TDC value selection

AM263P4: CAN TDC SDK Value selection

Marcel Pfeifer
Intellectual 355 points

Part Number: AM263P4
Other Parts Discussed in Thread: SYSCONFIG

Hey Experts,

ive a question regarding the TI example: mcan_external_read_write_am263px-cc_r5fss0-0_nortos_ti-arm-clang. Or even the whole SDK default settings for TDC.
There they use TDCO = 0x6 and TDCF = 0xA. I would asume to set the SSP similar to the first one around 70%-90%. So i would expect something like TDCO = 0xD. 
Can you explain why the values of TDCO and TDCF choosen the way they are?

Best regards,

Marcel

  • 0
    TI__Intellectual 2296 points

    Hey Marcel,

    The value of TDCO depends upon the delays in the end application but 6 is a good starting point. It also works for our examples and is a good value for most transceivers. Since it is a configurable value in SysConfig, the user is free to calculate and change it depending upon on the transceiver and bitrate in use.

    Regards,
    Pranav Siddappa

  • 0 in reply to Pranav Siddappa
    Intellectual 355 points

    Hey Pranav,

    based on my understanding TDCO hastn't to to anything with the delays in application and the transceiver. TDCO is added to TDCV, which is the measured delay. So TDCO is just used to set the samplepoint inside the recveided bit. Its set to 6, with a 80MHz clk at CAN, this means 75ns. One bit at 5Mbit bus speed is 200ns. So you sample at 37.5%. The normal sample point is set to 70%-90% to avoid the ringing at the begining of the bit. So its still not clear to me why you choose 37.5%. At the moment, it seems more like guesswork than an informed choice to me. 

    Regards,
    Marcel

  • +1 in reply to Marcel Pfeifer
    TI__Intellectual 2296 points

    Hey Marcel, 

    Sorry for the late reply. As you said Normal Sampling Point is supposed to be at 70-90%. However there is no such constraints set on the SSP. There no need for each bit to have an SSP point. The TRM specifies that the SSP point is supposed to be less than 6 bit time in data phase, which means the only constraint on SSP being that it is supposed to be placed at least once in 6 bits. 

    You calculated value of TDCV is 23. 
    Can clk : 80MHz
    Each quant is 25ns
    For data bitrate:
    - Prop Seg is 2
    - Phase Seg1 is 3
    - Phase Seg2 is 0

    Hence each bit is 6 quanta (1+2+3), 1 is for sync segment.
    TRM mentions that the TDCV+ TDCO value should be less than 6 bit time in data phase.
    So the TDCO+TDCV can be up to 6x6 -> 36 quanta.

    TDCV keeps varying and is decided by the transceiver. TDCO should be less than 13. Its not safe to set it as 13 since TDCV may spike and it might result in a bit error. So 6 feels like a safe value to give to TDCO when TDCV is 23.

    Above is the screenshot attached from the TRM.

    Regards,
    Pranav Siddappa