Hi All,
There appears to be a contridiciton between the operation text and the configuration example (One states the lower range at 10MHz, the other at 100MHz).
Page 264, 7.8 FPLL Operation "...a valid range on the output clock of 10MHz to 250MHz..."
Page 270, 7.11 FPLL Configuration Example "...The Output CLK of the PLL has to be in the range of 100MHz to 250MHz and the maximum Output CLK frequency does not exceed the maximum frequency of output divider PLL_DIV (device maximum frequency). ..."
Please confirm that the FPLL Output Clock Lower Range is actually 10MHz (as is per 7.8, and as coded in the F035 FPLL Calculator)?
Thanks,
Pete.
