Hi Team,
please kindly refer to the area highlighted in the figure below, since the specification does not define the upper and lower linits, please kindly help define the tolerence, or provide the complete upper and lower limit data,tks.


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Hi Team,
please kindly refer to the area highlighted in the figure below, since the specification does not define the upper and lower linits, please kindly help define the tolerence, or provide the complete upper and lower limit data,tks.


Hi Tommy, this device is obsolete on ti.com, please explain why you need this information.
Hi Joe,
not sure, only know it's OEM factory and that mass production is ongoing, inquire from the quality assurance division.
I've reached out to our packaging team to see if they can provide min/max specs.
Hi Joe,
got it, tks.
also, the customer concern as below:
The spacing between each pin is one of the factors that is related to the overhang issue.
Overhang means the percentage that foot of pin can be out of PCB's pad, please refer to the picture below for more information.
OSE wants to have the spacing information to have a further internal confirmation, because right now OSE is facing a overhang issue on this component.

Hello Tommy, the packaging team said the tolerance for this dimension is +/-0.20 mm

As to the pin to pin tolerance, our packaging expert was unable to find this in our documentation and has reached out to the vendor.
Hello Tommy, the vendor indicated the tolerance of lead pitch should be +/- 0.254mm
Hi Joe,
may we ask one more quesiton, if the lead frame pitch tolerance is +/-0.254mm, as sjown in datasheet below, is this consider reasonable for layout design? or should it be +/-0.0254mm?

Hi Tommy, the packaging team indicated there is no further clarification they can provide and that this header has been unchanged since its initial release in 2011.