Part Number: TMS570LC4357
Using processor TMS570LC4357 (Silicon Revision B), there is a problem with reading data over EMIF.
Data is read as 32 bits, i.e. two 16 bit words read for each data. Data copied from memory to CPU memory using is partly incorrect: the first 32-bit word copied in a copy loop is incorrect, the remainder are correct. Bus measurement shows that there is a single 16-bit access in preceeding the loop or initially in the loop, however we cannot see this from generated assembler code.
The EMIF uses CS4N in strobe mode with asynchronous wait enabled, with the following register settings: address 0xFCFFE804, data 0x000000FF, and address 0xFCFFE818, data 0xC4600301. When measuring EMIF accesses, it shows that after some correct 32-bit accesses, a single half 32-bit access (i.e., with the chip select active only once) occurs, followed by 32-bit accesses again. Additionally, when reading addresses such as 0x68090000 and upwards, reading offset 0x8 always returns incorrect data 0x0, but the subsequent read returns the correct data. If the offset 0x8 is read twice consecutively, the second read produces the correct value.
What could cause this except reading 16-bit data (which is not the case)? Are there any CPU registers which could help identify when and why the problem occurs?
Thanks
