Interrupts in TMS570

Hi sunil,

Thanks for the response.

Now i am not seeing any unexpected interrupt in my application.But in case if i come acorss any unexpected fault, my application should not stop.
It should continue what it is supposed to do i.e reading sensors and sending data on SPI.

I am combining questions related to other post which you replied also here

I am able to simulate single bit error and double bit error now.
I am seeing that during double bit error, the control goes to data abort ISR. But i would like to handle this double bit error
in the ISR routine i write. Is it possible ? I would like to route this error handling to VIM through ESM module. I have gone through the
TMS570 data sheet. and i have one doubut in table 4-2.

1. What is the difference between "RAM even bank (B0TCM) - uncorrectable error" [Group 2] and
   RAM even bank (B0TCM) - ECC uncorrectable error [Group 3] ?

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Coming to interrupt handling im TMS570.

I have simulated the data abort by making my program to access the Reserved memory. And the control passes to
data abort ISR correctly.

1. How to simulate the other interrupts that you have mentioned ? like undefined instrution, software interrupt, prefech abort.

2. I need my application to run continuosly though i these interrupts occur. How to do it ?

3. Is there any chance of occurence of interrupt which is not mentioned in VIM table, ESM table and the interrupts that you mentioned
   for TMs570 ? If so (i call these as unexpected interrupts),how to handle ?

Hi Bindu,

See my comments in blue below.

Regards, Sunil

I am seeing that during double bit error, the control goes to data abort ISR. But i would like to handle this double bit error
in the ISR routine i write. Is it possible?

>> This is not possible. A double-bit error on a CPU read from TCRAM causes a precise abort exception.

I would like to route this error handling to VIM through ESM module. I have gone through the
TMS570 data sheet. and i have one doubut in table 4-2.

1. What is the difference between "RAM even bank (B0TCM) - uncorrectable error" [Group 2] and
   RAM even bank (B0TCM) - ECC uncorrectable error [Group 3] ?

>> The TCRAM interface checks for three kinds of uncorrectable errors in the RAM:

1. Double-bit error indicated by CPU’s ECC logic: mapped to ESM group3 channel 3 or 5
2. Redundant address decode error: mapped to ESM group2 channel 6 or 8
3. Address and control bus parity error: mapped to ESM group2 channel 10 or 12

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Coming to interrupt handling im TMS570.

I have simulated the data abort by making my program to access the Reserved memory. And the control passes to
data abort ISR correctly.

1. How to simulate the other interrupts that you have mentioned ? like undefined instrution, software interrupt, prefech abort.

>> Undefined instruction: The ARM instruction set has an instruction called UDF that is "permanently undefined". That means that ARM will never define a valid instruction with the same encoding as the UDF instruction. You can make the processor execute the UDF instruction as follows. In a C file, add the following statement:

asm(" UDF #1");

The number "1" in the above statement can be any 16-bit number. This has no significance and is ignored by the processor.

It is recommended to fill all unused flash memory with a value that is recognized by the CPU as an undefined instruction. This allows the application to trap the CPU from executing invalid code in case of a pointer gone astray for example.

>> Software interrupt: Even if this is defined as an exception in the ARM architecture, the software interrupt (renamed as a Supervisor Call or SVC) is used mainly to define operations that are required to be done in Supervisor mode of the CPU. The microcontroller has several control registers that are not writable in user mode. If the CPU is in user mode and needs to configure one of these registers, it must first switch to the Supervisor mode. The SVC instruction allows the application to do just that. The encoding of the SVC instruction also allows the application to define a 24-bit (ARM instruction set) or 8-bit (Thumb2 instruction set) value which can then be used inside the SVC ISR to do different tasks based on this value.

>> A prefetch abort can be easily tested by attempting to execute an instruction from a non-existent memory location. The recommended instruction to return from a prefetch abort is "SUBS PC, LR_abt, #4". This instruction makes the processor execute the same instruction as the one that caused the abort. You need to manage the return instruction for the special case when you deliberately cause a prefetch abort just for testing it.

2. I need my application to run continuosly though i these interrupts occur. How to do it ?

>> The exceptions reset and abort are critical exceptions that will certainly affect the CPU's application code execution. Many peripherals (ADC, NHET, MibSPI) are autonomous to a large extent so that they can continue to perform while the CPU is servicing any exception.

3. Is there any chance of occurence of interrupt which is not mentioned in VIM table, ESM table and the interrupts that you mentioned
   for TMs570 ? If so (i call these as unexpected interrupts),how to handle ?

>> You need to have a defined response for all expected interrupts in your application.

Thanks Sunil for the detailed explanation. I have tried the options that you described in your response.

1) When use the asm(" UDF #1");in the C function, the assmbler throughs an error saying invalid menmonic. I searched for the UDF in the ARM architecture manual, but i could not find it. Let me know where you find it and how to remove this error.

2) I have simulated the SWI  as below.  I can see that control passes to SWI exception routine in the debug mode. When i hit Run button and pauses after some time, i see that the control is in the _memoryInit_ function waiting for the Hardware intialization to complete. Why is that ? I want the control to comeback to main program where the SWI_Error_Test is called. Is it possible ? If so,what chnages are required for exception routine.

void SWI_Error_Test (void)  {asm(" SWI #1");}

During debugging, after some time if do the CPU Reset, i have observed the same issue ( code waist for the hardware intialization to complete) If terminate the debugger and connect flash the code again, everything works fine. Any idea why ?

3) I have simulate the prefecth abort as below. I dont see that control passes to abort routine in the debug mode and also without debugger. Any idea what is going wrong ?

void Prefetch_Error_Test (void) {asm(" BKPT #1");}

1) When use the asm(" UDF #1");in the C function, the assmbler throughs an error saying invalid menmonic. I searched for the UDF in the ARM architecture manual, but i could not find it. Let me know where you find it and how to remove this error.

I made a mistake in assuming that the assembler already recognizes this mnemonic. You can use the instruction encoding, that is, 0xE7F000F0, to fill in unused program memory space. Also, you can make the CPU execute this instruction on purpose in order to generate an undefined instruction exception.

2) I have simulated the SWI  as below.  I can see that control passes to SWI exception routine in the debug mode. When i hit Run button and pauses after some time, i see that the control is in the _memoryInit_ function waiting for the Hardware intialization to complete. Why is that ? I want the control to comeback to main program where the SWI_Error_Test is called. Is it possible ? If so,what chnages are required for exception routine.

void SWI_Error_Test (void)  {asm(" SWI #1");}

During debugging, after some time if do the CPU Reset, i have observed the same issue ( code waist for the hardware intialization to complete) If terminate the debugger and connect flash the code again, everything works fine. Any idea why ?

You need to use the following statement to define the SWI exception routine as a special exception handler:

#pragma INTERRUPT (your_swi_handler_name, SWI);

This allows the compiler to treat this as a SWI handler and it will manage the CPU mode change back to the one when the SWI was called.

3) I have simulate the prefecth abort as below. I dont see that control passes to abort routine in the debug mode and also without debugger. Any idea what is going wrong ?

void Prefetch_Error_Test (void) {asm(" BKPT #1");}