1.DRAM 0 and 1 "sharing"
While working with PRU_0 and PRU_1, we were surprised at how it interacts with DRAM0 and DRAM1. We are writing c-code for both of these cores and based the linker files off of example code. After much experimentation, it was noted that PRU_0 data RAM address 0x00000000 goes to DRAM0 address 0x00000000, ICSS relative address 0x00000000. But unexpectedly, PRU_1 data RAM address 0x00000000 goes to DRAM1 address 0x00000000, ICSS relative address 0x00002000. Both linker files use a starting RAM address of 0x00000000 and a length of 0x2000 for the data ram. We also noted that PRU_0 is able to access DRAM1 by referencing addresses greater than 0x2000. We also noted that PRU_1 was never able to directly make use of DRAM0. This is surprising, as the technical reference manual describes DRAM0 and DRAM1 as being shared.
2. DRAM2 access outside of ICSS
We were able to determine that DRAM2 could be utilized by both cores of the PRU as expected, and data could be exchanged between PRU_0 and PRU_1 in this region. However, we were unable to use R5 core 0_0 to read or write values to 0x48010000 as expected. What is really interesting is that if R5 core 0_0 writes to 0x48010000 it can correctly read that value back, however, neither PRU core is able to retrieve the value from 0x00010000. We are truly confused as to what R5 core 0_0 is actually writing to in these instances. We have also validated that the MPU is setup correctly to allow read/write operations to this region.
3. CCS display of PRU stack values
This doesn't work. None of our local variables find the correctly memory address when debugging in CCS. We were able to track down variable memory locations by walking through the assembly code to determine that they were being handled in RAM correctly.
4. CCS display of DRAM2 in memory viewer
When either of the PRU cores is selected during a debug session, and the memory window is set to PRU_Device_Memory, all of the values at 0x00010000 (DRAM2) show as 0. We have written test code to read/write directly to values in this region and validated that data flow is as expected, its just not being displayed in the memory viewer.
5. Technical Reference Manual error
In section 2.3 of SPRUJ55D (latest AM263P Technical Reference Manual), it lists PRU-ICSS Data RAM2 as starting at 0x00010000 and ending at 0x0001FFFF as expected. but it lists this size as 64KB, which it is not. We believe this should be 32KB to align with the listed locations and other areas of the document describing the size of DRAM2.
Please provide clarifications that what we have observed through development testing is what TI expects but hasn't clearly documented in the Technical Reference Manual.
